From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: Re: [PATCH v5 06/15] target/riscv: zicfilp `lpad` impl and branch tracking
Date: Tue, 20 Aug 2024 15:29:52 +1000 [thread overview]
Message-ID: <04082b27-3c3c-4a1c-9416-c8feb2319c6d@linaro.org> (raw)
In-Reply-To: <20240820000129.3522346-7-debug@rivosinc.com>
On 8/20/24 10:01, Deepak Gupta wrote:
> Implements setting lp expected when `jalr` is encountered and implements
> `lpad` instruction of zicfilp. `lpad` instruction is taken out of
> auipc x0, <imm_20>. This is an existing HINTNOP space. If `lpad` is
> target of an indirect branch, cpu checks for 20 bit value in x7 upper
> with 20 bit value embedded in `lpad`. If they don't match, cpu raises a
> sw check exception with tval = 2.
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> Co-developed-by: Jim Shu <jim.shu@sifive.com>
> Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
> ---
> target/riscv/cpu_user.h | 1 +
> target/riscv/insn32.decode | 5 ++-
> target/riscv/insn_trans/trans_rvi.c.inc | 55 +++++++++++++++++++++++++
> 3 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_user.h b/target/riscv/cpu_user.h
> index 02afad608b..e6927ff847 100644
> --- a/target/riscv/cpu_user.h
> +++ b/target/riscv/cpu_user.h
> @@ -15,5 +15,6 @@
> #define xA6 16
> #define xA7 17 /* syscall number for RVI ABI */
> #define xT0 5 /* syscall number for RVE ABI */
> +#define xT2 7
>
> #endif
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index c45b8fa1d8..6533cb0758 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -123,7 +123,10 @@ sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
>
> # *** RV32I Base Instruction Set ***
> lui .................... ..... 0110111 @u
> -auipc .................... ..... 0010111 @u
> +{
> + lpad label:20 00000 0010111
> + auipc .................... ..... 0010111 @u
> +}
> jal .................... ..... 1101111 @j
Again, best to line up the decode bits.
While you are required to add two spaces within { },
you can remove two spaces before the first '.':
lui .................... ..... 0110111 @u
{
lpad label:20 00000 0010111
auipc .................... ..... 0010111 @u
}
jal .................... ..... 1101111 @j
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2024-08-20 5:30 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-20 0:01 [PATCH v5 00/15] riscv support for control flow integrity extensions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 01/15] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 02/15] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-20 5:17 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 03/15] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 04/15] target/riscv: additional code information for sw check Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 05/15] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-20 5:24 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 06/15] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-20 5:29 ` Richard Henderson [this message]
2024-08-20 0:01 ` [PATCH v5 07/15] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 08/15] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 09/15] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-20 5:34 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 10/15] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 11/15] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-20 7:35 ` Deepak Gupta
2024-08-20 9:20 ` Richard Henderson
2024-08-20 18:55 ` Deepak Gupta
2024-08-20 19:45 ` Deepak Gupta
2024-08-20 22:33 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 12/15] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 13/15] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 14/15] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 15/15] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
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