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[189.204.159.168]) by smtp.gmail.com with ESMTPSA id i3sm1918836oov.2.2021.03.26.07.19.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 26 Mar 2021 07:19:08 -0700 (PDT) Subject: Re: [PATCH] target/arm: Make number of counters in PMCR follow the CPU To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20210311165947.27470-1-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <0409d14a-85ac-aed6-1867-5ee95a3926ca@linaro.org> Date: Fri, 26 Mar 2021 08:19:05 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: <20210311165947.27470-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x336.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcin Juszkiewicz , Leif Lindholm Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/11/21 10:59 AM, Peter Maydell wrote: > Currently we give all the v7-and-up CPUs a PMU with 4 counters. This > means that we don't provide the 6 counters that are required by the > Arm BSA (Base System Architecture) specification if the CPU supports > the Virtualization extensions. > > Instead of having a single PMCR_NUM_COUNTERS, make each CPU type > specify the PMCR reset value (obtained from the appropriate TRM), and > use the 'N' field of that value to define the number of counters > provided. > > This means that we now supply 6 counters for Cortex-A53, A57, A72, > A15 and A9 as well as '-cpu max'; Cortex-A7 and A8 stay at 4; and > Cortex-R5 goes down to 3. > > Note that because we now use the PMCR reset value of the specific > implementation, we no longer set the LC bit out of reset. This has > an UNKNOWN value out of reset for all cores with any AArch32 support, > so guest software should be setting it anyway if it wants it. > > Signed-off-by: Peter Maydell > --- > This is pretty much untested (I just checked Linux still boots; > haven't tried it with KVM either). It's an alternative to > just bumping PMCR_NUM_COUNTERS to 6. > --- > target/arm/cpu.h | 1 + > target/arm/cpu64.c | 3 +++ > target/arm/cpu_tcg.c | 5 +++++ > target/arm/helper.c | 29 +++++++++++++++++------------ > target/arm/kvm64.c | 2 ++ > 5 files changed, 28 insertions(+), 12 deletions(-) Reviewed-by: Richard Henderson r~