From: "Cédric Le Goater" <clg@kaod.org>
To: Kane Chen <kane_chen@aspeedtech.com>,
Peter Maydell <peter.maydell@linaro.org>,
Steven Lee <steven_lee@aspeedtech.com>,
Troy Lee <leetroy@gmail.com>,
Jamin Lin <jamin_lin@aspeedtech.com>,
Andrew Jeffery <andrew@codeconstruct.com.au>,
Joel Stanley <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: Troy Lee <troy_lee@aspeedtech.com>
Subject: Re: [PATCH v2 0/3] Add QEMU model for ASPEED OTP memory and integrate with SoC
Date: Fri, 27 Jun 2025 11:23:25 +0200 [thread overview]
Message-ID: <042961e9-d61b-41e1-b1fd-3adc2cfa9cff@kaod.org> (raw)
In-Reply-To: <SI6PR06MB76312CBD36E8204DA851E454F745A@SI6PR06MB7631.apcprd06.prod.outlook.com>
On 6/27/25 11:09, Kane Chen wrote:
> Hi Cédric,
>
> Thanks for your reviewing and comments.
>
> Regarding the drive property and block backend, my understanding is that the following changes would be required:
>
> 1. Add a BlockBackend field in AspeedOTPState
> 2. Register a drive property to associate the backend with the device
Let's do 1. and 2. first.
The rest has been discussed already in previous emails.
Please go through them.
Thanks,
C.
prev parent reply other threads:[~2025-06-27 9:24 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-27 2:56 [PATCH v2 0/3] Add QEMU model for ASPEED OTP memory and integrate with SoC Kane Chen via
2025-06-27 2:56 ` [PATCH v2 1/3] hw/misc/aspeed_otp: Add ASPEED OTP memory device model Kane Chen via
2025-06-27 2:56 ` [PATCH v2 2/3] hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC Kane Chen via
2025-06-27 6:48 ` Cédric Le Goater
2025-06-27 2:56 ` [PATCH v2 3/3] hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs Kane Chen via
2025-06-27 6:52 ` [PATCH v2 0/3] Add QEMU model for ASPEED OTP memory and integrate with SoC Cédric Le Goater
2025-06-27 9:09 ` Kane Chen
2025-06-27 9:23 ` Cédric Le Goater [this message]
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