Re: [PATCH 2/2] tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions

["Cédric Le Goater" <clg@kaod.org>]

On 4/13/23 21:01, Shivaprasad G Bhat wrote:
> Add test for vextractbm, vextractwm, vextractdm and vextractqm
> instructions. Test works for both qemu-ppc64 and qemu-ppc64le.
> 
> Based on the test case written by John Platts posted at [1]
> 
> References:
> [1]: https://gitlab.com/qemu-project/qemu/-/issues/1536

Gitlab issues should be referenced as :

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1536

However, this patch adds a test, not a fix. So it is the previous patch
which should be annotated as resolving the issue.

Also, I think the code should be using  HOST_BIG_ENDIAN instead of
__ORDER_BIG_ENDIAN__

Thanks,

C.

> 
> Signed-off-by: John Platts <john_platts@hotmail.com>
> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
> ---
>   tests/tcg/ppc64/Makefile.target |    6 ++++-
>   tests/tcg/ppc64/vector.c        |   50 +++++++++++++++++++++++++++++++++++++++
>   2 files changed, 55 insertions(+), 1 deletion(-)
>   create mode 100644 tests/tcg/ppc64/vector.c
> 
> diff --git a/tests/tcg/ppc64/Makefile.target b/tests/tcg/ppc64/Makefile.target
> index f081f1c683..4fd543ce28 100644
> --- a/tests/tcg/ppc64/Makefile.target
> +++ b/tests/tcg/ppc64/Makefile.target
> @@ -20,7 +20,7 @@ PPC64_TESTS += mtfsf
>   PPC64_TESTS += mffsce
>   
>   ifneq ($(CROSS_CC_HAS_POWER10),)
> -PPC64_TESTS += byte_reverse sha512-vector
> +PPC64_TESTS += byte_reverse sha512-vector vector
>   endif
>   byte_reverse: CFLAGS += -mcpu=power10
>   run-byte_reverse: QEMU_OPTS+=-cpu POWER10
> @@ -33,6 +33,10 @@ sha512-vector: sha512.c
>   run-sha512-vector: QEMU_OPTS+=-cpu POWER10
>   run-plugin-sha512-vector-with-%: QEMU_OPTS+=-cpu POWER10
>   
> +vector: CFLAGS += -mcpu=power10
> +run-vector: QEMU_OPTS += -cpu POWER10
> +run-plugin-vector-with-%: QEMU_OPTS += -cpu POWER10
> +
>   PPC64_TESTS += signal_save_restore_xer
>   PPC64_TESTS += xxspltw
>   
> diff --git a/tests/tcg/ppc64/vector.c b/tests/tcg/ppc64/vector.c
> new file mode 100644
> index 0000000000..3cb2b88c87
> --- /dev/null
> +++ b/tests/tcg/ppc64/vector.c
> @@ -0,0 +1,50 @@
> +#include <assert.h>
> +#include <stdint.h>
> +
> +int main(void)
> +{
> +    unsigned int result_wi;
> +    vector unsigned char vbc_bi_src = { 0xFF, 0xFF, 0, 0xFF, 0xFF, 0xFF,
> +                                        0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0,
> +                                        0, 0xFF, 0xFF};
> +    vector unsigned short vbc_hi_src = { 0xFFFF, 0, 0, 0xFFFF,
> +                                         0, 0, 0xFFFF, 0xFFFF};
> +    vector unsigned int vbc_wi_src = {0, 0, 0xFFFFFFFF, 0xFFFFFFFF};
> +    vector unsigned long long vbc_di_src = {0xFFFFFFFFFFFFFFFF, 0};
> +    vector __uint128_t vbc_qi_src;
> +
> +    asm("vextractbm %0, %1" : "=r" (result_wi) : "v" (vbc_bi_src));
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +    assert(result_wi == 0b1101111111000011);
> +#else
> +    assert(result_wi == 0b1100001111111011);
> +#endif
> +
> +    asm("vextracthm %0, %1" : "=r" (result_wi) : "v" (vbc_hi_src));
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +    assert(result_wi == 0b10010011);
> +#else
> +    assert(result_wi == 0b11001001);
> +#endif
> +
> +    asm("vextractwm %0, %1" : "=r" (result_wi) : "v" (vbc_wi_src));
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +    assert(result_wi == 0b0011);
> +#else
> +    assert(result_wi == 0b1100);
> +#endif
> +
> +    asm("vextractdm %0, %1" : "=r" (result_wi) : "v" (vbc_di_src));
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +    assert(result_wi == 0b10);
> +#else
> +    assert(result_wi == 0b01);
> +#endif
> +
> +    vbc_qi_src[0] = 0x1;
> +    vbc_qi_src[0] = vbc_qi_src[0] << 127;
> +    asm("vextractqm %0, %1" : "=r" (result_wi) : "v" (vbc_qi_src));
> +    assert(result_wi == 0b1);
> +
> +    return 0;
> +}
> 
>