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From: Richard Henderson <rth@twiddle.net>
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Date: Mon, 26 Sep 2016 14:50:58 -0700
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Subject: Re: [Qemu-devel] [PATCH 02/18] target-riscv: Add RISC-V Target
 stubs inside target-riscv/
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To: Sagar Karandikar <sagark@eecs.berkeley.edu>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, kbastian@mail.uni-paderborn.de

On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
> +typedef struct CPURISCVState CPURISCVState;
> +struct CPURISCVState {
> +    target_ulong gpr[32];
> +    uint64_t fpr[32]; /* assume both F and D extensions */
> +    target_ulong PC;
> +    target_ulong load_res;
> +
> +    target_ulong csr[4096]; /* RISCV CSR registers */

This is 16k for 32-bit, and 32k for 64-bit, most of which is unused.

I think it would be better to add only the CSRs that you actually need for the 
implementation.


r~