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Fri, 15 Aug 2025 07:30:59 -0700 (PDT) Received: from [192.168.4.112] ([206.83.105.236]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76e4526a1fasm1257160b3a.13.2025.08.15.07.30.57 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Aug 2025 07:30:59 -0700 (PDT) Message-ID: <04500975-6a94-4bf9-b362-a0f310060dbc@linaro.org> Date: Sat, 16 Aug 2025 00:30:54 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC 2/3] target/ppc: Add IBM PPE42 special instructions To: qemu-devel@nongnu.org References: <20250814223741.29433-1-milesg@linux.ibm.com> <20250814223741.29433-3-milesg@linux.ibm.com> From: Richard Henderson Content-Language: en-US In-Reply-To: <20250814223741.29433-3-milesg@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/15/25 08:37, Glenn Miles wrote: > Adds the following instructions exclusively for > IBM PPE42 processors: > > LSKU > LCXU > STSKU > STCXU > LVD > LVDU > LVDX > STVD > STVDU > STVDX > SLVD > SRVD > CMPWBC > CMPLWBC > CMPWIBC > BNBWI > BNBW > CLRBWIBC > CLRWBC > DCBQ > RLDICL > RLDICR > RLDIMI > > A PPE42 GCC compiler is available here: > https://github.com/open-power/ppe42-gcc > > For more information on the PPE42 processors please visit: > https://wiki.raptorcs.com/w/images/a/a3/PPE_42X_Core_Users_Manual.pdf > > Signed-off-by: Glenn Miles > --- > target/ppc/helper_regs.c | 15 +- > target/ppc/insn32.decode | 66 ++- > target/ppc/translate.c | 29 +- > target/ppc/translate/ppe-impl.c.inc | 805 ++++++++++++++++++++++++++++ > 4 files changed, 898 insertions(+), 17 deletions(-) > create mode 100644 target/ppc/translate/ppe-impl.c.inc Oof. This is really too much at once -- the patch ought to be split. > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index e53fd2840d..8beb588a2a 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -58,6 +58,10 @@ > %ds_rtp 22:4 !function=times_2 > @DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si > > +%dd_si 3:s13 Note that the format describes this as shifted left by 3. I see you multiply by 8 in trans_LSKU, but it's generally easier to have the immediates match the format description. > +&DD rt ra si:int64_t Why are you forcing si to int64_t? It's a 16-bit signed immediate. > +static bool trans_LCXU(DisasContext *ctx, arg_LCXU *a) > +{ > +#if defined(TARGET_PPC64) > + return false; > +#else > + int i; > + TCGv base, EA; > + TCGv lo, hi; > + TCGv_i64 t8; > + const uint8_t vd_list[] = {9, 7, 5, 3, 0}; We're trying to move away from having separate binaries for different cpu models. While target/ppc/ needs quite a bit of work for that to be a reality, let's try to avoid adding more code that needs cleaning up. > + > + if (unlikely(!is_ppe(ctx))) { > + return false; > + } This test should be sufficient to disable the insn for ppc64, without the ifdef. r~