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From: David Hildenbrand <david@redhat.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH v4 06/16] tcg/s390x: Implement tcg_out_mov for vector types
Date: Tue, 14 Sep 2021 18:53:49 +0200	[thread overview]
Message-ID: <045600e5-a3bf-18f3-b8a8-9e593c97a3ed@redhat.com> (raw)
In-Reply-To: <20210626050307.2408505-7-richard.henderson@linaro.org>

On 26.06.21 07:02, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/s390x/tcg-target.c.inc | 72 +++++++++++++++++++++++++++++++++++---
>   1 file changed, 68 insertions(+), 4 deletions(-)
> 
> diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
> index b6ea129e14..c4e12a57f3 100644
> --- a/tcg/s390x/tcg-target.c.inc
> +++ b/tcg/s390x/tcg-target.c.inc
> @@ -265,6 +265,11 @@ typedef enum S390Opcode {
>       RX_STC      = 0x42,
>       RX_STH      = 0x40,
>   
> +    VRRa_VLR    = 0xe756,
> +
> +    VRSb_VLVG   = 0xe722,
> +    VRSc_VLGV   = 0xe721,
> +
>       VRX_VL      = 0xe706,
>       VRX_VLLEZ   = 0xe704,
>       VRX_VST     = 0xe70e,
> @@ -548,6 +553,39 @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
>            | ((v4 & 0x10) << (4 + 0));
>   }
>   
> +static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op,
> +                              TCGReg v1, TCGReg v2, int m3)
> +{
> +    tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31);
> +    tcg_debug_assert(v2 >= TCG_REG_V0 && v2 <= TCG_REG_V31);
> +    tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15));
> +    tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12));
> +}
> +
> +static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1,
> +                              intptr_t d2, TCGReg b2, TCGReg r3, int m4)
> +{
> +    tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31);
> +    tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
> +    tcg_debug_assert(b2 <= TCG_REG_R15);
> +    tcg_debug_assert(r3 <= TCG_REG_R15);
> +    tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | r3);
> +    tcg_out16(s, b2 << 12 | d2);
> +    tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12));
> +}
> +
> +static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1,
> +                              intptr_t d2, TCGReg b2, TCGReg v3, int m4)
> +{
> +    tcg_debug_assert(r1 <= TCG_REG_R15);
> +    tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
> +    tcg_debug_assert(b2 <= TCG_REG_R15);
> +    tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31);
> +    tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 15));
> +    tcg_out16(s, b2 << 12 | d2);
> +    tcg_out16(s, (op & 0x00ff) | RXB(0, 0, v3, 0) | (m4 << 12));
> +}
> +
>   static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1,
>                                TCGReg b2, TCGReg x2, intptr_t d2, int m3)
>   {
> @@ -581,12 +619,38 @@ static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
>   
>   static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
>   {
> -    if (src != dst) {
> -        if (type == TCG_TYPE_I32) {
> +    if (src == dst) {
> +        return true;
> +    }
> +    switch (type) {
> +    case TCG_TYPE_I32:
> +        if (likely(dst < 16 && src < 16)) {
>               tcg_out_insn(s, RR, LR, dst, src);
> -        } else {
> -            tcg_out_insn(s, RRE, LGR, dst, src);
> +            break;
>           }
> +        /* fallthru */
> +

Does that fall-through work as expected? I would have thought we would 
want to pass "2" as m4 for VLGV and VLVG below?

Apart from that LGTM.


-- 
Thanks,

David / dhildenb



  reply	other threads:[~2021-09-14 16:55 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-26  5:02 [PATCH v4 00/16] tcg/s390x: host vector support Richard Henderson
2021-06-26  5:02 ` [PATCH v4 01/16] tcg/s390x: Rename from tcg/s390 Richard Henderson
2021-06-26  5:02 ` [PATCH v4 02/16] tcg/s390x: Change FACILITY representation Richard Henderson
2021-06-26  5:02 ` [PATCH v4 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg Richard Henderson
2021-06-26  5:02 ` [PATCH v4 04/16] tcg/s390x: Add host vector framework Richard Henderson
2021-09-14 16:27   ` David Hildenbrand
2021-06-26  5:02 ` [PATCH v4 05/16] tcg/s390x: Implement tcg_out_ld/st for vector types Richard Henderson
2021-09-14 16:46   ` David Hildenbrand
2021-09-14 22:02     ` Richard Henderson
2021-09-14 22:03     ` Richard Henderson
2021-09-14 22:14       ` Richard Henderson
2021-09-15 13:22         ` David Hildenbrand
2021-06-26  5:02 ` [PATCH v4 06/16] tcg/s390x: Implement tcg_out_mov " Richard Henderson
2021-09-14 16:53   ` David Hildenbrand [this message]
2021-09-14 16:56     ` David Hildenbrand
2021-06-26  5:02 ` [PATCH v4 07/16] tcg/s390x: Implement tcg_out_dup*_vec Richard Henderson
2021-06-26  5:02 ` [PATCH v4 08/16] tcg/s390x: Implement minimal vector operations Richard Henderson
2021-09-14 17:59   ` David Hildenbrand
2021-06-26  5:03 ` [PATCH v4 09/16] tcg/s390x: Implement andc, orc, abs, neg, not " Richard Henderson
2021-09-14 17:37   ` David Hildenbrand
2021-06-26  5:03 ` [PATCH v4 10/16] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec Richard Henderson
2021-09-14 17:38   ` David Hildenbrand
2021-06-26  5:03 ` [PATCH v4 11/16] tcg/s390x: Implement vector shift operations Richard Henderson
2021-09-14 17:40   ` David Hildenbrand
2021-06-26  5:03 ` [PATCH v4 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
2021-09-14 17:42   ` David Hildenbrand
2021-06-26  5:03 ` [PATCH v4 13/16] tcg: Expand usadd/ussub with umin/umax Richard Henderson
2021-06-26  5:03 ` [PATCH v4 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
2021-06-26  5:03 ` [PATCH v4 15/16] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec Richard Henderson
2021-06-26  5:03 ` [PATCH v4 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec Richard Henderson
2021-06-26  5:24 ` [PATCH v4 00/16] tcg/s390x: host vector support no-reply
2021-09-12 21:57 ` Richard Henderson

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