From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:53364) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMXab-0006ZM-WC for qemu-devel@nongnu.org; Fri, 03 May 2019 08:46:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMXaa-0006Qn-Uz for qemu-devel@nongnu.org; Fri, 03 May 2019 08:46:57 -0400 References: <20190502141019.6385-1-david@redhat.com> <20190502141019.6385-3-david@redhat.com> <69b8508d-9586-ab11-3318-83d21ddd4d25@linaro.org> From: David Hildenbrand Message-ID: <045f9c87-858c-507d-a8ae-01ccff9c3cab@redhat.com> Date: Fri, 3 May 2019 14:46:51 +0200 MIME-Version: 1.0 In-Reply-To: <69b8508d-9586-ab11-3318-83d21ddd4d25@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 02/40] s390x/tcg: Implement VECTOR ADD COMPUTE CARRY List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Cornelia Huck , Thomas Huth , Richard Henderson On 03.05.19 05:45, Richard Henderson wrote: > On 5/2/19 7:09 AM, David Hildenbrand wrote: >> 128-bit handling courtesy of Richard H. >> >> Signed-off-by: David Hildenbrand >> --- >> target/s390x/insn-data.def | 2 + >> target/s390x/translate_vx.inc.c | 94 +++++++++++++++++++++++++++++++++ >> 2 files changed, 96 insertions(+) > > Reviewed-by: Richard Henderson > >> +static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es) >> +{ >> + const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1; >> + TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr)); >> + TCGv_i64 t1 = tcg_temp_new_i64(); >> + TCGv_i64 t2 = tcg_temp_new_i64(); >> + TCGv_i64 t3 = tcg_temp_new_i64(); >> + >> + /* Calculate the carry into the MSB, ignoring the old MSBs */ >> + tcg_gen_andc_i64(t1, a, msb_mask); >> + tcg_gen_andc_i64(t2, b, msb_mask); >> + tcg_gen_add_i64(t1, t1, t2); >> + /* Calculate the MSB without any carry into it */ >> + tcg_gen_xor_i64(t3, a, b); >> + /* Calculate the carry out of the MSB in the MSB bit position */ >> + tcg_gen_and_i64(d, a, b); >> + tcg_gen_and_i64(t1, t1, t3); >> + tcg_gen_or_i64(d, d, t1); >> + /* Isolate and shift the carry into position */ >> + tcg_gen_and_i64(d, d, msb_mask); >> + tcg_gen_shri_i64(d, d, msb_bit_nr); >> + >> + tcg_temp_free_i64(t1); >> + tcg_temp_free_i64(t2); >> + tcg_temp_free_i64(t3); >> +} > ...> +static void gen_acc32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) >> +{ >> + gen_acc(d, a, b, ES_32); >> +} >> + >> +static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) >> +{ >> + TCGv_i64 t = tcg_temp_new_i64(); >> + >> + tcg_gen_add_i64(t, a, b); >> + tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b); >> + tcg_temp_free_i64(t); >> +} > > As an aside, I think the 32-bit version should use 32-bit ops, as per > gen_acc_i64. That would be 4 * 2 operations instead of 2 * 9 over the 128-bit > vector. Makes sense, thanks! > > > r~ > -- Thanks, David / dhildenb From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A726C004C9 for ; Fri, 3 May 2019 12:48:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E5CAE2075E for ; Fri, 3 May 2019 12:48:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E5CAE2075E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([127.0.0.1]:40273 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMXcS-0007Nm-1g for qemu-devel@archiver.kernel.org; Fri, 03 May 2019 08:48:52 -0400 Received: from eggs.gnu.org ([209.51.188.92]:53364) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMXab-0006ZM-WC for qemu-devel@nongnu.org; Fri, 03 May 2019 08:46:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMXaa-0006Qn-Uz for qemu-devel@nongnu.org; Fri, 03 May 2019 08:46:57 -0400 Received: from mx1.redhat.com ([209.132.183.28]:53938) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hMXaa-0006Pi-JE; Fri, 03 May 2019 08:46:56 -0400 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1699930715CA; Fri, 3 May 2019 12:46:55 +0000 (UTC) Received: from [10.36.116.157] (ovpn-116-157.ams2.redhat.com [10.36.116.157]) by smtp.corp.redhat.com (Postfix) with ESMTP id B52985DA34; Fri, 3 May 2019 12:46:52 +0000 (UTC) To: Richard Henderson , qemu-devel@nongnu.org References: <20190502141019.6385-1-david@redhat.com> <20190502141019.6385-3-david@redhat.com> <69b8508d-9586-ab11-3318-83d21ddd4d25@linaro.org> From: David Hildenbrand Openpgp: preference=signencrypt Autocrypt: addr=david@redhat.com; prefer-encrypt=mutual; keydata= xsFNBFXLn5EBEAC+zYvAFJxCBY9Tr1xZgcESmxVNI/0ffzE/ZQOiHJl6mGkmA1R7/uUpiCjJ dBrn+lhhOYjjNefFQou6478faXE6o2AhmebqT4KiQoUQFV4R7y1KMEKoSyy8hQaK1umALTdL QZLQMzNE74ap+GDK0wnacPQFpcG1AE9RMq3aeErY5tujekBS32jfC/7AnH7I0v1v1TbbK3Gp XNeiN4QroO+5qaSr0ID2sz5jtBLRb15RMre27E1ImpaIv2Jw8NJgW0k/D1RyKCwaTsgRdwuK Kx/Y91XuSBdz0uOyU/S8kM1+ag0wvsGlpBVxRR/xw/E8M7TEwuCZQArqqTCmkG6HGcXFT0V9 PXFNNgV5jXMQRwU0O/ztJIQqsE5LsUomE//bLwzj9IVsaQpKDqW6TAPjcdBDPLHvriq7kGjt WhVhdl0qEYB8lkBEU7V2Yb+SYhmhpDrti9Fq1EsmhiHSkxJcGREoMK/63r9WLZYI3+4W2rAc UucZa4OT27U5ZISjNg3Ev0rxU5UH2/pT4wJCfxwocmqaRr6UYmrtZmND89X0KigoFD/XSeVv jwBRNjPAubK9/k5NoRrYqztM9W6sJqrH8+UWZ1Idd/DdmogJh0gNC0+N42Za9yBRURfIdKSb B3JfpUqcWwE7vUaYrHG1nw54pLUoPG6sAA7Mehl3nd4pZUALHwARAQABzSREYXZpZCBIaWxk ZW5icmFuZCA8ZGF2aWRAcmVkaGF0LmNvbT7CwX4EEwECACgFAljj9eoCGwMFCQlmAYAGCwkI BwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJEE3eEPcA/4Na5IIP/3T/FIQMxIfNzZshIq687qgG 8UbspuE/YSUDdv7r5szYTK6KPTlqN8NAcSfheywbuYD9A4ZeSBWD3/NAVUdrCaRP2IvFyELj xoMvfJccbq45BxzgEspg/bVahNbyuBpLBVjVWwRtFCUEXkyazksSv8pdTMAs9IucChvFmmq3 jJ2vlaz9lYt/lxN246fIVceckPMiUveimngvXZw21VOAhfQ+/sofXF8JCFv2mFcBDoa7eYob s0FLpmqFaeNRHAlzMWgSsP80qx5nWWEvRLdKWi533N2vC/EyunN3HcBwVrXH4hxRBMco3jvM m8VKLKao9wKj82qSivUnkPIwsAGNPdFoPbgghCQiBjBe6A75Z2xHFrzo7t1jg7nQfIyNC7ez MZBJ59sqA9EDMEJPlLNIeJmqslXPjmMFnE7Mby/+335WJYDulsRybN+W5rLT5aMvhC6x6POK z55fMNKrMASCzBJum2Fwjf/VnuGRYkhKCqqZ8gJ3OvmR50tInDV2jZ1DQgc3i550T5JDpToh dPBxZocIhzg+MBSRDXcJmHOx/7nQm3iQ6iLuwmXsRC6f5FbFefk9EjuTKcLMvBsEx+2DEx0E UnmJ4hVg7u1PQ+2Oy+Lh/opK/BDiqlQ8Pz2jiXv5xkECvr/3Sv59hlOCZMOaiLTTjtOIU7Tq 7ut6OL64oAq+zsFNBFXLn5EBEADn1959INH2cwYJv0tsxf5MUCghCj/CA/lc/LMthqQ773ga uB9mN+F1rE9cyyXb6jyOGn+GUjMbnq1o121Vm0+neKHUCBtHyseBfDXHA6m4B3mUTWo13nid 0e4AM71r0DS8+KYh6zvweLX/LL5kQS9GQeT+QNroXcC1NzWbitts6TZ+IrPOwT1hfB4WNC+X 2n4AzDqp3+ILiVST2DT4VBc11Gz6jijpC/KI5Al8ZDhRwG47LUiuQmt3yqrmN63V9wzaPhC+ xbwIsNZlLUvuRnmBPkTJwwrFRZvwu5GPHNndBjVpAfaSTOfppyKBTccu2AXJXWAE1Xjh6GOC 8mlFjZwLxWFqdPHR1n2aPVgoiTLk34LR/bXO+e0GpzFXT7enwyvFFFyAS0Nk1q/7EChPcbRb hJqEBpRNZemxmg55zC3GLvgLKd5A09MOM2BrMea+l0FUR+PuTenh2YmnmLRTro6eZ/qYwWkC u8FFIw4pT0OUDMyLgi+GI1aMpVogTZJ70FgV0pUAlpmrzk/bLbRkF3TwgucpyPtcpmQtTkWS gDS50QG9DR/1As3LLLcNkwJBZzBG6PWbvcOyrwMQUF1nl4SSPV0LLH63+BrrHasfJzxKXzqg rW28CTAE2x8qi7e/6M/+XXhrsMYG+uaViM7n2je3qKe7ofum3s4vq7oFCPsOgwARAQABwsFl BBgBAgAPBQJVy5+RAhsMBQkJZgGAAAoJEE3eEPcA/4NagOsP/jPoIBb/iXVbM+fmSHOjEshl KMwEl/m5iLj3iHnHPVLBUWrXPdS7iQijJA/VLxjnFknhaS60hkUNWexDMxVVP/6lbOrs4bDZ NEWDMktAeqJaFtxackPszlcpRVkAs6Msn9tu8hlvB517pyUgvuD7ZS9gGOMmYwFQDyytpepo YApVV00P0u3AaE0Cj/o71STqGJKZxcVhPaZ+LR+UCBZOyKfEyq+ZN311VpOJZ1IvTExf+S/5 lqnciDtbO3I4Wq0ArLX1gs1q1XlXLaVaA3yVqeC8E7kOchDNinD3hJS4OX0e1gdsx/e6COvy qNg5aL5n0Kl4fcVqM0LdIhsubVs4eiNCa5XMSYpXmVi3HAuFyg9dN+x8thSwI836FoMASwOl C7tHsTjnSGufB+D7F7ZBT61BffNBBIm1KdMxcxqLUVXpBQHHlGkbwI+3Ye+nE6HmZH7IwLwV W+Ajl7oYF+jeKaH4DZFtgLYGLtZ1LDwKPjX7VAsa4Yx7S5+EBAaZGxK510MjIx6SGrZWBrrV TEvdV00F2MnQoeXKzD7O4WFbL55hhyGgfWTHwZ457iN9SgYi1JLPqWkZB0JRXIEtjd4JEQcx +8Umfre0Xt4713VxMygW0PnQt5aSQdMD58jHFxTk092mU+yIHj5LeYgvwSgZN4airXk5yRXl SE+xAvmumFBY Organization: Red Hat GmbH Message-ID: <045f9c87-858c-507d-a8ae-01ccff9c3cab@redhat.com> Date: Fri, 3 May 2019 14:46:51 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <69b8508d-9586-ab11-3318-83d21ddd4d25@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.49]); Fri, 03 May 2019 12:46:55 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: Re: [Qemu-devel] [PATCH v3 02/40] s390x/tcg: Implement VECTOR ADD COMPUTE CARRY X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Thomas Huth , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Message-ID: <20190503124651.VZ38NsFczNt6gOXnpCap09U5CHrPq4sMv6WoX0-ZkCk@z> On 03.05.19 05:45, Richard Henderson wrote: > On 5/2/19 7:09 AM, David Hildenbrand wrote: >> 128-bit handling courtesy of Richard H. >> >> Signed-off-by: David Hildenbrand >> --- >> target/s390x/insn-data.def | 2 + >> target/s390x/translate_vx.inc.c | 94 +++++++++++++++++++++++++++++++++ >> 2 files changed, 96 insertions(+) > > Reviewed-by: Richard Henderson > >> +static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, uint8_t es) >> +{ >> + const uint8_t msb_bit_nr = NUM_VEC_ELEMENT_BITS(es) - 1; >> + TCGv_i64 msb_mask = tcg_const_i64(dup_const(es, 1ull << msb_bit_nr)); >> + TCGv_i64 t1 = tcg_temp_new_i64(); >> + TCGv_i64 t2 = tcg_temp_new_i64(); >> + TCGv_i64 t3 = tcg_temp_new_i64(); >> + >> + /* Calculate the carry into the MSB, ignoring the old MSBs */ >> + tcg_gen_andc_i64(t1, a, msb_mask); >> + tcg_gen_andc_i64(t2, b, msb_mask); >> + tcg_gen_add_i64(t1, t1, t2); >> + /* Calculate the MSB without any carry into it */ >> + tcg_gen_xor_i64(t3, a, b); >> + /* Calculate the carry out of the MSB in the MSB bit position */ >> + tcg_gen_and_i64(d, a, b); >> + tcg_gen_and_i64(t1, t1, t3); >> + tcg_gen_or_i64(d, d, t1); >> + /* Isolate and shift the carry into position */ >> + tcg_gen_and_i64(d, d, msb_mask); >> + tcg_gen_shri_i64(d, d, msb_bit_nr); >> + >> + tcg_temp_free_i64(t1); >> + tcg_temp_free_i64(t2); >> + tcg_temp_free_i64(t3); >> +} > ...> +static void gen_acc32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) >> +{ >> + gen_acc(d, a, b, ES_32); >> +} >> + >> +static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) >> +{ >> + TCGv_i64 t = tcg_temp_new_i64(); >> + >> + tcg_gen_add_i64(t, a, b); >> + tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b); >> + tcg_temp_free_i64(t); >> +} > > As an aside, I think the 32-bit version should use 32-bit ops, as per > gen_acc_i64. That would be 4 * 2 operations instead of 2 * 9 over the 128-bit > vector. Makes sense, thanks! > > > r~ > -- Thanks, David / dhildenb