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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-718e5968a09sm3673287b3a.117.2024.09.09.08.45.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Sep 2024 08:45:55 -0700 (PDT) Message-ID: <0475550c-53c4-4166-bb04-1ff21f5d11b9@linaro.org> Date: Mon, 9 Sep 2024 08:45:52 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 02/14] util: Add RISC-V vector extension probe in cpuinfo To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng References: <20240904142739.854-1-zhiwei_liu@linux.alibaba.com> <20240904142739.854-3-zhiwei_liu@linux.alibaba.com> <286685da-74e3-401a-afe4-fed0831fd97c@linaro.org> <5fc48f87-b233-40b9-a0e1-4de920d97957@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <5fc48f87-b233-40b9-a0e1-4de920d97957@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/9/24 00:18, LIU Zhiwei wrote: > > On 2024/9/5 11:34, Richard Henderson wrote: >> On 9/4/24 07:27, LIU Zhiwei wrote: >>> +    if (info & CPUINFO_ZVE64X) { >>> +        /* >>> +         * Get vlenb for Vector: vsetvli rd, x0, e64. >>> +         * VLMAX = LMUL * VLEN / SEW. >>> +         * The "vsetvli rd, x0, e64" means "LMUL = 1, SEW = 64, rd = VLMAX", >>> +         * so "vlenb = VLMAX * 64 / 8". >>> +         */ >>> +        unsigned long vlmax = 0; >>> +        asm volatile(".insn i 0x57, 7, %0, zero, (3 << 3)" : "=r"(vlmax)); >>> +        if (vlmax) { >>> +            riscv_vlenb = vlmax * 8; >>> +            assert(riscv_vlen >= 64 && !(riscv_vlen & (riscv_vlen - 1))); >>> +        } else { >>> +            info &= ~CPUINFO_ZVE64X; >>> +        } >>> +    } >> >> Surely this does not compile, since the riscv_vlen referenced in the assert does not exist. > riscv_vlen is macro about riscv_vlenb. I think you miss it. I did miss the macro. But there's also no need for it to exist. >> >> That said, I've done some experimentation and I believe there is a further >> simplification to be had in instead saving log2(vlenb). >> >>     if (info & CPUINFO_ZVE64X) { >>         /* >>          * We are guaranteed by RVV-1.0 that VLEN is a power of 2. >>          * We are guaranteed by Zve64x that VLEN >= 64, and that >>          * EEW of {8,16,32,64} are supported. >>          * >>          * Cache VLEN in a convenient form. >>          */ >>         unsigned long vlenb; >>         asm("csrr %0, vlenb" : "=r"(vlenb)); > > Should we use the .insn format here? Maybe we are having a compiler doesn't support vector. Neither gcc nor clang requires V be enabled at compile time in order to access the CSR. It does seem like a mistake, but I'm happy to use it. r~