From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>,
peter.maydell@linaro.org
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com,
palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org
Subject: Re: [RFC PATCH 2/8] riscv: Generate payload scripts
Date: Wed, 20 May 2020 17:06:39 +0800 [thread overview]
Message-ID: <04f42926-1b47-b433-3f52-23cda14ad478@c-sky.com> (raw)
In-Reply-To: <865aaf91-59da-09a3-438a-3230ff69d093@linaro.org>
On 2020/5/20 13:41, Richard Henderson wrote:
> On 5/19/20 7:37 PM, LIU Zhiwei wrote:
>> On 2020/5/12 1:40, Richard Henderson wrote:
>>> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>>>> + # sequence of li rd, 0x1234567887654321
>>>> + #
>>>> + # 0: 002471b7 lui rd,0x247
>>>> + # 4: 8ad1819b addiw rd,rd,-1875
>>>> + # 8: 00c19193 slli rd,rd,0xc
>>>> + # c: f1118193 addi rd,rd,-239 # 0x246f11
>>>> + # 10: 00d19193 slli rd,rd,0xd
>>>> + # 14: d9518193 addi rd,rd,-619
>>>> + # 18: 00e19193 slli rd,rd,0xe
>>>> + # 1c: 32118193 addi rd,rd,801
>>> You don't really need to use addiw. Removing that special case would really
>>> simplify this.
>> I think I don't get it. Do you mean that the immediate will not be 64 bit?
> Well, mostly the immediate will be small, actually. But the interface must
> support 64-bit immediates.
>
> I'm saying that for this computation,
>
> lui
> addi
> slli
> addi
> ...
>
> is the same. You don't *have* to use addiw.
I see addiw is not good, as it is a RV64 only instruction. I think addi
is right and better.
But I'm afraid I don't get
"Removing that special case would really
simplify this."
Do you mean I need not the decode_li function if I use addi instead of
addiw?
Zhiwei
>
> r~
next prev parent reply other threads:[~2020-05-20 9:11 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 7:21 [RFC PATCH 0/8] RISCV risu porting LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 1/8] riscv: Add RV64I instructions description LIU Zhiwei
2020-05-11 16:39 ` Richard Henderson
2020-05-20 2:41 ` LIU Zhiwei
2020-05-20 5:39 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 2/8] riscv: Generate payload scripts LIU Zhiwei
2020-05-11 17:40 ` Richard Henderson
2020-05-20 2:37 ` LIU Zhiwei
2020-05-20 5:41 ` Richard Henderson
2020-05-20 9:06 ` LIU Zhiwei [this message]
2020-04-30 7:21 ` [RFC PATCH 3/8] riscv: Define riscv struct reginfo LIU Zhiwei
2020-05-11 17:42 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 4/8] riscv: Implement payload load interfaces LIU Zhiwei
2020-05-11 18:03 ` Richard Henderson
2020-05-11 18:07 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 5/8] riscv: Add standard test case LIU Zhiwei
2020-05-11 18:04 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 6/8] riscv: Add configure script LIU Zhiwei
2020-05-11 18:06 ` Richard Henderson
2020-05-20 1:45 ` LIU Zhiwei
2020-05-20 2:28 ` LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 7/8] riscv: Add RV64M instructions description LIU Zhiwei
2020-05-11 18:12 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 8/8] riscv: Add RV64F " LIU Zhiwei
2020-05-11 18:11 ` Richard Henderson
2020-05-19 12:27 ` LIU Zhiwei
2020-05-11 16:30 ` [RFC PATCH 0/8] RISCV risu porting Richard Henderson
2020-05-19 9:44 ` LIU Zhiwei
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