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Mon, 25 May 2020 19:02:10 +0000 (UTC) Subject: Re: [PATCH] hw/block/pflash_cfi01: Limit maximum flash size to 256 MiB To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org References: <20200525155826.11333-1-philmd@redhat.com> From: Laszlo Ersek Message-ID: <0520c681-a6f9-5bcd-ca7d-4ad92e4d4764@redhat.com> Date: Mon, 25 May 2020 21:02:09 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20200525155826.11333-1-philmd@redhat.com> Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=205.139.110.120; envelope-from=lersek@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/25 01:44:10 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Peter Maydell , Tanmay Jagdale , qemu-block@nongnu.org, Hongbo Zhang , Radoslaw Biernacki , Markus Armbruster , Max Reitz , Leif Lindholm Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 05/25/20 17:58, Philippe Mathieu-Daudé wrote: > As of this commit, the biggest CFI01 NOR flash documented is > the Micron PC28F00BP33EF. Its size is 2 GiB (256 MiB). I don't understand what "2 GiB (256 MiB)" means; please clarify. > > Actually this "2Gb device employs a virtual chip enable feature, > which combines two 1Gb die with a common chip enable". > > Since we do not want to model unrealistic hardware, cap the > current model to this maximum. At least we have a datasheet > to refer. > > If a bigger flash is provided, the user get this warning: > > qemu-system-aarch64: Initialization of device cfi.pflash01 failed: Maximum supported CFI flash size is 16 MiB. > > Note, the sbsa-ref ARM machine introduced in commit 64580903c2b > already uses a pair of 256 MiB flash devices. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/block/pflash_cfi01.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c > index 11922c0f96..40f145dde7 100644 > --- a/hw/block/pflash_cfi01.c > +++ b/hw/block/pflash_cfi01.c > @@ -37,6 +37,8 @@ > */ > > #include "qemu/osdep.h" > +#include "qemu/units.h" > +#include "qemu/cutils.h" > #include "hw/block/block.h" > #include "hw/block/flash.h" > #include "hw/qdev-properties.h" > @@ -68,6 +70,8 @@ do { \ > #define PFLASH_BE 0 > #define PFLASH_SECURE 1 > > +#define PFLASH_SIZE_MAX (256 * MiB) /* Micron PC28F00BP33EF */ > + > struct PFlashCFI01 { > /*< private >*/ > SysBusDevice parent_obj; > @@ -717,6 +721,12 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) > } > > total_len = pfl->sector_len * pfl->nb_blocs; > + if (total_len > PFLASH_SIZE_MAX) { > + char *maxsz = size_to_str(PFLASH_SIZE_MAX); > + error_setg(errp, "Maximum supported CFI flash size is %s.", maxsz); > + g_free(maxsz); > + return; > + } > > /* These are only used to expose the parameters of each device > * in the cfi_table[]. > I'm unsure how strong the argument is, "we do not want to model unrealistic hardware", but I do think the patch does what it says on the tin (modulo the one part in the commit message that I don't understand). With the commit message clarified Reviewed-by: Laszlo Ersek (I expect & hope people will provide better reviews than mine.) Thanks Laszlo