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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id gc1sm3868883pjb.20.2020.02.11.08.56.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Feb 2020 08:56:15 -0800 (PST) Subject: Re: [PATCH v4 4/4] target/riscv: add vector configure instruction To: LIU Zhiwei , alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com References: <20200210081240.11481-1-zhiwei_liu@c-sky.com> <20200210081240.11481-5-zhiwei_liu@c-sky.com> From: Richard Henderson Message-ID: <053777e2-7180-5584-cf7f-7876800d9dc8@linaro.org> Date: Tue, 11 Feb 2020 08:56:13 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200210081240.11481-5-zhiwei_liu@c-sky.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/10/20 8:12 AM, LIU Zhiwei wrote: > static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, > - target_ulong *cs_base, uint32_t *flags) > + target_ulong *cs_base, uint32_t *pflags) > { > + uint32_t flags = 0; > + uint32_t vlmax; > + uint8_t vl_eq_vlmax; bool. > + > *pc = env->pc; > *cs_base = 0; > + > + if (env->misa & RVV) { > + vlmax = vext_get_vlmax(env_archcpu(env), env->vext.vtype); > + vl_eq_vlmax = (env->vext.vstart == 0) && (vlmax == env->vext.vl); You might as well move the variable declarations inside this block. > +target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, > + target_ulong s2) Indentation. > +{ > + int vlmax, vl; > + RISCVCPU *cpu = env_archcpu(env); > + uint16_t sew = 1 << FIELD_EX64(s2, VTYPE, SEW); > + > + if (sew > cpu->cfg.elen) { /* only set vill bit. */ > + env->vext.vtype = FIELD_DP64(0, VTYPE, VILL, 1); > + env->vext.vl = 0; > + env->vext.vstart = 0; > + return 0; > + } You're missing checks against EDIV, VILL and the RESERVED field == 0. > + > + vlmax = vext_get_vlmax(cpu, s2); > + if (s1 <= vlmax) { > + vl = s1; > + } else { > + vl = vlmax; > + } > + env->vext.vl = vl; > + env->vext.vtype = s2; > + env->vext.vstart = 0; > + return vl; > +} > r~