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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, Alistair.Francis@wdc.com
Subject: Re: [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions
Date: Tue, 7 Jan 2025 11:29:14 +0100	[thread overview]
Message-ID: <05497e58-43ad-41de-b868-223aafa6ed3e@linaro.org> (raw)
In-Reply-To: <20250102181601.1421059-3-richard.henderson@linaro.org>

Hi Richard,

On 2/1/25 19:16, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/riscv/tcg-target-has.h |  8 +++++++-
>   tcg/riscv/tcg-target.c.inc | 13 +++++++++++--
>   2 files changed, 18 insertions(+), 3 deletions(-)
> 
> diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h
> index 10e61edc45..ea38ee5cbb 100644
> --- a/tcg/riscv/tcg-target-has.h
> +++ b/tcg/riscv/tcg-target-has.h
> @@ -64,7 +64,13 @@ tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
>           /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */
>           return ofs || (cpuinfo & CPUINFO_ZBA);
>       }
> -    return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && len == 16;
> +    switch (len) {
> +    case 1:
> +        return (cpuinfo & CPUINFO_ZBS) && ofs != 0;

Why can't we have ofs=0?

> +    case 16:
> +        return (cpuinfo & CPUINFO_ZBB) && ofs == 0;
> +    }
> +    return false;
>   }
>   #define TCG_TARGET_extract_valid  tcg_target_extract_valid
>   
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 12c3cffcc0..83ec7cd980 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -162,6 +162,7 @@ typedef enum {
>       OPC_ANDI = 0x7013,
>       OPC_AUIPC = 0x17,
>       OPC_BEQ = 0x63,
> +    OPC_BEXTI = 0x48005013,
>       OPC_BGE = 0x5063,
>       OPC_BGEU = 0x7063,
>       OPC_BLT = 0x4063,
> @@ -2307,9 +2308,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
>               } else {
>                   tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
>               }
> -        } else if (a2 == 0 && args[3] == 16) {
> +            break;
> +        }
> +        switch (args[3]) {
> +        case 1:
> +            tcg_out_opc_imm(s, OPC_BEXTI, a0, a1, a2);
> +            break;
> +        case 16:
> +            tcg_debug_assert(a2 == 0);
>               tcg_out_ext16u(s, a0, a1);
> -        } else {
> +            break;
> +        default:
>               g_assert_not_reached();
>           }
>           break;



  parent reply	other threads:[~2025-01-07 10:29 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-02 18:15 [PATCH 0/2] tcg/riscv: Use BEXTI for single-bit extractions Richard Henderson
2025-01-02 18:16 ` [PATCH 1/2] util/cpuinfo-riscv: Detect Zbs Richard Henderson
2025-01-06  0:44   ` Alistair Francis
2025-01-07  9:05   ` Philippe Mathieu-Daudé
2025-01-02 18:16 ` [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions Richard Henderson
2025-01-06  0:45   ` Alistair Francis
2025-01-07 10:29   ` Philippe Mathieu-Daudé [this message]
2025-01-07 15:27     ` Richard Henderson

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