* [PATCH 0/2] tcg/riscv: Use BEXTI for single-bit extractions
@ 2025-01-02 18:15 Richard Henderson
2025-01-02 18:16 ` [PATCH 1/2] util/cpuinfo-riscv: Detect Zbs Richard Henderson
2025-01-02 18:16 ` [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions Richard Henderson
0 siblings, 2 replies; 8+ messages in thread
From: Richard Henderson @ 2025-01-02 18:15 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-riscv, palmer, Alistair.Francis
Based-on: 20250102180654.1420056-1-richard.henderson@linaro.org
("[PATCH 00/73] tcg: Merge *_i32 and *_i64 opcodes")
While riscv does not yet have a completely general extract,
the Zbs extension added a single-bit extract.
Tested on cfarm95, a Banana Pi BPI-F3.
r~
Richard Henderson (2):
util/cpuinfo-riscv: Detect Zbs
tcg/riscv: Use BEXTI for single-bit extractions
host/include/riscv/host/cpuinfo.h | 5 +++--
tcg/riscv/tcg-target-has.h | 8 +++++++-
util/cpuinfo-riscv.c | 18 ++++++++++++++++--
tcg/riscv/tcg-target.c.inc | 13 +++++++++++--
4 files changed, 37 insertions(+), 7 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/2] util/cpuinfo-riscv: Detect Zbs 2025-01-02 18:15 [PATCH 0/2] tcg/riscv: Use BEXTI for single-bit extractions Richard Henderson @ 2025-01-02 18:16 ` Richard Henderson 2025-01-06 0:44 ` Alistair Francis 2025-01-07 9:05 ` Philippe Mathieu-Daudé 2025-01-02 18:16 ` [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions Richard Henderson 1 sibling, 2 replies; 8+ messages in thread From: Richard Henderson @ 2025-01-02 18:16 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-riscv, palmer, Alistair.Francis Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- host/include/riscv/host/cpuinfo.h | 5 +++-- util/cpuinfo-riscv.c | 18 ++++++++++++++++-- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpuinfo.h index cdc784e7b6..b2b53dbf62 100644 --- a/host/include/riscv/host/cpuinfo.h +++ b/host/include/riscv/host/cpuinfo.h @@ -9,8 +9,9 @@ #define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ #define CPUINFO_ZBA (1u << 1) #define CPUINFO_ZBB (1u << 2) -#define CPUINFO_ZICOND (1u << 3) -#define CPUINFO_ZVE64X (1u << 4) +#define CPUINFO_ZBS (1u << 3) +#define CPUINFO_ZICOND (1u << 4) +#define CPUINFO_ZVE64X (1u << 5) /* Initialized with a constructor. */ extern unsigned cpuinfo; diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c index 971c924012..0291b7218a 100644 --- a/util/cpuinfo-riscv.c +++ b/util/cpuinfo-riscv.c @@ -36,7 +36,8 @@ static void sigill_handler(int signo, siginfo_t *si, void *data) /* Called both as constructor and (possibly) via other constructors. */ unsigned __attribute__((constructor)) cpuinfo_init(void) { - unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND | CPUINFO_ZVE64X; + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZBS + | CPUINFO_ZICOND | CPUINFO_ZVE64X; unsigned info = cpuinfo; if (info) { @@ -50,6 +51,9 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) #if defined(__riscv_arch_test) && defined(__riscv_zbb) info |= CPUINFO_ZBB; #endif +#if defined(__riscv_arch_test) && defined(__riscv_zbs) + info |= CPUINFO_ZBS; +#endif #if defined(__riscv_arch_test) && defined(__riscv_zicond) info |= CPUINFO_ZICOND; #endif @@ -71,7 +75,8 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) && pair.key >= 0) { info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; - left &= ~(CPUINFO_ZBA | CPUINFO_ZBB); + info |= pair.value & RISCV_HWPROBE_EXT_ZBS ? CPUINFO_ZBS : 0; + left &= ~(CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZBS); #ifdef RISCV_HWPROBE_EXT_ZICOND info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; left &= ~CPUINFO_ZICOND; @@ -117,6 +122,15 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) left &= ~CPUINFO_ZBB; } + if (left & CPUINFO_ZBS) { + /* Probe for Zbs: bext zero,zero,zero. */ + got_sigill = 0; + asm volatile(".insn r 0x33, 5, 0x24, zero, zero, zero" + : : : "memory"); + info |= got_sigill ? 0 : CPUINFO_ZBS; + left &= ~CPUINFO_ZBS; + } + if (left & CPUINFO_ZICOND) { /* Probe for Zicond: czero.eqz zero,zero,zero. */ got_sigill = 0; -- 2.43.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] util/cpuinfo-riscv: Detect Zbs 2025-01-02 18:16 ` [PATCH 1/2] util/cpuinfo-riscv: Detect Zbs Richard Henderson @ 2025-01-06 0:44 ` Alistair Francis 2025-01-07 9:05 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 8+ messages in thread From: Alistair Francis @ 2025-01-06 0:44 UTC (permalink / raw) To: Richard Henderson; +Cc: qemu-devel, qemu-riscv, palmer, Alistair.Francis On Fri, Jan 3, 2025 at 4:28 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > host/include/riscv/host/cpuinfo.h | 5 +++-- > util/cpuinfo-riscv.c | 18 ++++++++++++++++-- > 2 files changed, 19 insertions(+), 4 deletions(-) > > diff --git a/host/include/riscv/host/cpuinfo.h b/host/include/riscv/host/cpuinfo.h > index cdc784e7b6..b2b53dbf62 100644 > --- a/host/include/riscv/host/cpuinfo.h > +++ b/host/include/riscv/host/cpuinfo.h > @@ -9,8 +9,9 @@ > #define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */ > #define CPUINFO_ZBA (1u << 1) > #define CPUINFO_ZBB (1u << 2) > -#define CPUINFO_ZICOND (1u << 3) > -#define CPUINFO_ZVE64X (1u << 4) > +#define CPUINFO_ZBS (1u << 3) > +#define CPUINFO_ZICOND (1u << 4) > +#define CPUINFO_ZVE64X (1u << 5) > > /* Initialized with a constructor. */ > extern unsigned cpuinfo; > diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c > index 971c924012..0291b7218a 100644 > --- a/util/cpuinfo-riscv.c > +++ b/util/cpuinfo-riscv.c > @@ -36,7 +36,8 @@ static void sigill_handler(int signo, siginfo_t *si, void *data) > /* Called both as constructor and (possibly) via other constructors. */ > unsigned __attribute__((constructor)) cpuinfo_init(void) > { > - unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZICOND | CPUINFO_ZVE64X; > + unsigned left = CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZBS > + | CPUINFO_ZICOND | CPUINFO_ZVE64X; > unsigned info = cpuinfo; > > if (info) { > @@ -50,6 +51,9 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) > #if defined(__riscv_arch_test) && defined(__riscv_zbb) > info |= CPUINFO_ZBB; > #endif > +#if defined(__riscv_arch_test) && defined(__riscv_zbs) > + info |= CPUINFO_ZBS; > +#endif > #if defined(__riscv_arch_test) && defined(__riscv_zicond) > info |= CPUINFO_ZICOND; > #endif > @@ -71,7 +75,8 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) > && pair.key >= 0) { > info |= pair.value & RISCV_HWPROBE_EXT_ZBA ? CPUINFO_ZBA : 0; > info |= pair.value & RISCV_HWPROBE_EXT_ZBB ? CPUINFO_ZBB : 0; > - left &= ~(CPUINFO_ZBA | CPUINFO_ZBB); > + info |= pair.value & RISCV_HWPROBE_EXT_ZBS ? CPUINFO_ZBS : 0; > + left &= ~(CPUINFO_ZBA | CPUINFO_ZBB | CPUINFO_ZBS); > #ifdef RISCV_HWPROBE_EXT_ZICOND > info |= pair.value & RISCV_HWPROBE_EXT_ZICOND ? CPUINFO_ZICOND : 0; > left &= ~CPUINFO_ZICOND; > @@ -117,6 +122,15 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) > left &= ~CPUINFO_ZBB; > } > > + if (left & CPUINFO_ZBS) { > + /* Probe for Zbs: bext zero,zero,zero. */ > + got_sigill = 0; > + asm volatile(".insn r 0x33, 5, 0x24, zero, zero, zero" > + : : : "memory"); > + info |= got_sigill ? 0 : CPUINFO_ZBS; > + left &= ~CPUINFO_ZBS; > + } > + > if (left & CPUINFO_ZICOND) { > /* Probe for Zicond: czero.eqz zero,zero,zero. */ > got_sigill = 0; > -- > 2.43.0 > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] util/cpuinfo-riscv: Detect Zbs 2025-01-02 18:16 ` [PATCH 1/2] util/cpuinfo-riscv: Detect Zbs Richard Henderson 2025-01-06 0:44 ` Alistair Francis @ 2025-01-07 9:05 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2025-01-07 9:05 UTC (permalink / raw) To: Richard Henderson, qemu-devel; +Cc: qemu-riscv, palmer, Alistair.Francis On 2/1/25 19:16, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > host/include/riscv/host/cpuinfo.h | 5 +++-- > util/cpuinfo-riscv.c | 18 ++++++++++++++++-- > 2 files changed, 19 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions 2025-01-02 18:15 [PATCH 0/2] tcg/riscv: Use BEXTI for single-bit extractions Richard Henderson 2025-01-02 18:16 ` [PATCH 1/2] util/cpuinfo-riscv: Detect Zbs Richard Henderson @ 2025-01-02 18:16 ` Richard Henderson 2025-01-06 0:45 ` Alistair Francis 2025-01-07 10:29 ` Philippe Mathieu-Daudé 1 sibling, 2 replies; 8+ messages in thread From: Richard Henderson @ 2025-01-02 18:16 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-riscv, palmer, Alistair.Francis Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/riscv/tcg-target-has.h | 8 +++++++- tcg/riscv/tcg-target.c.inc | 13 +++++++++++-- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h index 10e61edc45..ea38ee5cbb 100644 --- a/tcg/riscv/tcg-target-has.h +++ b/tcg/riscv/tcg-target-has.h @@ -64,7 +64,13 @@ tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */ return ofs || (cpuinfo & CPUINFO_ZBA); } - return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && len == 16; + switch (len) { + case 1: + return (cpuinfo & CPUINFO_ZBS) && ofs != 0; + case 16: + return (cpuinfo & CPUINFO_ZBB) && ofs == 0; + } + return false; } #define TCG_TARGET_extract_valid tcg_target_extract_valid diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 12c3cffcc0..83ec7cd980 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -162,6 +162,7 @@ typedef enum { OPC_ANDI = 0x7013, OPC_AUIPC = 0x17, OPC_BEQ = 0x63, + OPC_BEXTI = 0x48005013, OPC_BGE = 0x5063, OPC_BGEU = 0x7063, OPC_BLT = 0x4063, @@ -2307,9 +2308,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, } else { tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2); } - } else if (a2 == 0 && args[3] == 16) { + break; + } + switch (args[3]) { + case 1: + tcg_out_opc_imm(s, OPC_BEXTI, a0, a1, a2); + break; + case 16: + tcg_debug_assert(a2 == 0); tcg_out_ext16u(s, a0, a1); - } else { + break; + default: g_assert_not_reached(); } break; -- 2.43.0 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions 2025-01-02 18:16 ` [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions Richard Henderson @ 2025-01-06 0:45 ` Alistair Francis 2025-01-07 10:29 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 8+ messages in thread From: Alistair Francis @ 2025-01-06 0:45 UTC (permalink / raw) To: Richard Henderson; +Cc: qemu-devel, qemu-riscv, palmer, Alistair.Francis On Fri, Jan 3, 2025 at 4:21 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > tcg/riscv/tcg-target-has.h | 8 +++++++- > tcg/riscv/tcg-target.c.inc | 13 +++++++++++-- > 2 files changed, 18 insertions(+), 3 deletions(-) > > diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h > index 10e61edc45..ea38ee5cbb 100644 > --- a/tcg/riscv/tcg-target-has.h > +++ b/tcg/riscv/tcg-target-has.h > @@ -64,7 +64,13 @@ tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) > /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */ > return ofs || (cpuinfo & CPUINFO_ZBA); > } > - return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && len == 16; > + switch (len) { > + case 1: > + return (cpuinfo & CPUINFO_ZBS) && ofs != 0; > + case 16: > + return (cpuinfo & CPUINFO_ZBB) && ofs == 0; > + } > + return false; > } > #define TCG_TARGET_extract_valid tcg_target_extract_valid > > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 12c3cffcc0..83ec7cd980 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -162,6 +162,7 @@ typedef enum { > OPC_ANDI = 0x7013, > OPC_AUIPC = 0x17, > OPC_BEQ = 0x63, > + OPC_BEXTI = 0x48005013, > OPC_BGE = 0x5063, > OPC_BGEU = 0x7063, > OPC_BLT = 0x4063, > @@ -2307,9 +2308,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > } else { > tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2); > } > - } else if (a2 == 0 && args[3] == 16) { > + break; > + } > + switch (args[3]) { > + case 1: > + tcg_out_opc_imm(s, OPC_BEXTI, a0, a1, a2); > + break; > + case 16: > + tcg_debug_assert(a2 == 0); > tcg_out_ext16u(s, a0, a1); > - } else { > + break; > + default: > g_assert_not_reached(); > } > break; > -- > 2.43.0 > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions 2025-01-02 18:16 ` [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions Richard Henderson 2025-01-06 0:45 ` Alistair Francis @ 2025-01-07 10:29 ` Philippe Mathieu-Daudé 2025-01-07 15:27 ` Richard Henderson 1 sibling, 1 reply; 8+ messages in thread From: Philippe Mathieu-Daudé @ 2025-01-07 10:29 UTC (permalink / raw) To: Richard Henderson, qemu-devel; +Cc: qemu-riscv, palmer, Alistair.Francis Hi Richard, On 2/1/25 19:16, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/riscv/tcg-target-has.h | 8 +++++++- > tcg/riscv/tcg-target.c.inc | 13 +++++++++++-- > 2 files changed, 18 insertions(+), 3 deletions(-) > > diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h > index 10e61edc45..ea38ee5cbb 100644 > --- a/tcg/riscv/tcg-target-has.h > +++ b/tcg/riscv/tcg-target-has.h > @@ -64,7 +64,13 @@ tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) > /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */ > return ofs || (cpuinfo & CPUINFO_ZBA); > } > - return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && len == 16; > + switch (len) { > + case 1: > + return (cpuinfo & CPUINFO_ZBS) && ofs != 0; Why can't we have ofs=0? > + case 16: > + return (cpuinfo & CPUINFO_ZBB) && ofs == 0; > + } > + return false; > } > #define TCG_TARGET_extract_valid tcg_target_extract_valid > > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index 12c3cffcc0..83ec7cd980 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -162,6 +162,7 @@ typedef enum { > OPC_ANDI = 0x7013, > OPC_AUIPC = 0x17, > OPC_BEQ = 0x63, > + OPC_BEXTI = 0x48005013, > OPC_BGE = 0x5063, > OPC_BGEU = 0x7063, > OPC_BLT = 0x4063, > @@ -2307,9 +2308,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > } else { > tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2); > } > - } else if (a2 == 0 && args[3] == 16) { > + break; > + } > + switch (args[3]) { > + case 1: > + tcg_out_opc_imm(s, OPC_BEXTI, a0, a1, a2); > + break; > + case 16: > + tcg_debug_assert(a2 == 0); > tcg_out_ext16u(s, a0, a1); > - } else { > + break; > + default: > g_assert_not_reached(); > } > break; ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions 2025-01-07 10:29 ` Philippe Mathieu-Daudé @ 2025-01-07 15:27 ` Richard Henderson 0 siblings, 0 replies; 8+ messages in thread From: Richard Henderson @ 2025-01-07 15:27 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: qemu-riscv, palmer, Alistair.Francis On 1/7/25 02:29, Philippe Mathieu-Daudé wrote: > Hi Richard, > > On 2/1/25 19:16, Richard Henderson wrote: >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> tcg/riscv/tcg-target-has.h | 8 +++++++- >> tcg/riscv/tcg-target.c.inc | 13 +++++++++++-- >> 2 files changed, 18 insertions(+), 3 deletions(-) >> >> diff --git a/tcg/riscv/tcg-target-has.h b/tcg/riscv/tcg-target-has.h >> index 10e61edc45..ea38ee5cbb 100644 >> --- a/tcg/riscv/tcg-target-has.h >> +++ b/tcg/riscv/tcg-target-has.h >> @@ -64,7 +64,13 @@ tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) >> /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */ >> return ofs || (cpuinfo & CPUINFO_ZBA); >> } >> - return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && len == 16; >> + switch (len) { >> + case 1: >> + return (cpuinfo & CPUINFO_ZBS) && ofs != 0; > > Why can't we have ofs=0? To prefer ANDI. r~ ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-01-07 15:27 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-01-02 18:15 [PATCH 0/2] tcg/riscv: Use BEXTI for single-bit extractions Richard Henderson 2025-01-02 18:16 ` [PATCH 1/2] util/cpuinfo-riscv: Detect Zbs Richard Henderson 2025-01-06 0:44 ` Alistair Francis 2025-01-07 9:05 ` Philippe Mathieu-Daudé 2025-01-02 18:16 ` [PATCH 2/2] tcg/riscv: Use BEXTI for single-bit extractions Richard Henderson 2025-01-06 0:45 ` Alistair Francis 2025-01-07 10:29 ` Philippe Mathieu-Daudé 2025-01-07 15:27 ` Richard Henderson
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