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[156.19.246.23]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-734a0024d4bsm2452535b3a.104.2025.02.27.16.18.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Feb 2025 16:18:50 -0800 (PST) Message-ID: <05633317-0484-4595-94e5-c7fddbb2d283@linaro.org> Date: Thu, 27 Feb 2025 16:18:47 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] target/arm: Correct LDRD atomicity and fault behaviour To: Peter Maydell Cc: qemu-devel@nongnu.org References: <20250227142746.1698904-1-peter.maydell@linaro.org> <20250227142746.1698904-2-peter.maydell@linaro.org> <69ae459d-90ff-441d-a039-ae3ee15c919e@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/27/25 09:58, Peter Maydell wrote: > On Thu, 27 Feb 2025 at 17:41, Richard Henderson > wrote: >> >> On 2/27/25 06:27, Peter Maydell wrote: >>> +static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2) >>> +{ >>> + /* >>> + * LDRD is required to be an atomic 64-bit access if the >>> + * address is 8-aligned, two atomic 32-bit accesses if >>> + * it's only 4-aligned, and to give an alignemnt fault >>> + * if it's not 4-aligned. >>> + * Rt is always the word from the lower address, and Rt2 the >>> + * data from the higher address, regardless of endianness. >>> + * So (like gen_load_exclusive) we avoid gen_aa32_ld_i64() >>> + * so we don't get its SCTLR_B check, and instead do a 64-bit access >>> + * using MO_BE if appropriate and then split the two halves. >>> + * >>> + * This also gives us the correct behaviour of not updating >>> + * rt if the load of rt2 faults; this is required for cases >>> + * like "ldrd r2, r3, [r2]" where rt is also the base register. >>> + */ >>> + int mem_idx = get_mem_index(s); >>> + MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data; >> >> The 64-bit atomicity begins with armv7 + LPAE, and not present for any m-profile. >> Worth checking ARM_FEATURE_LPAE, or at least adding to the comment? >> >> Getting 2 x 4-byte atomicity, but not require 8-byte atomicity, would use >> MO_ATOM_IFALIGN_PAIR. > > Definitely worth a comment at minimum. Do we generate better > code for MO_ATOM_IFALIGN_PAIR ? (If not, then providing higher > atomicity than the architecture mandates seems harmless.) We could, but currently do not, generate better code for IFALIGN_PAIR for MO_64. Currently the only place we take special care is for MO_128. > For the comment in memop.h that currently reads > * MO_ATOM_SUBALIGN: the operation is single-copy atomic by parts > * by the alignment. E.g. if the address is 0 mod 4, then each > * 4-byte subobject is single-copy atomic. > * This is the atomicity e.g. of IBM Power. > > maybe we could expand the e.g: > > E.g if an 8-byte value is accessed at an address which is 0 mod 8, > then the whole 8-byte access is single-copy atomic; otherwise, > if it is accessed at 0 mod 4 then each 4-byte subobject is > single-copy atomic; otherwise if it is accessed at 0 mod 2 > then the four 2-byte subobjects are single-copy atomic. > > ? Yes, that's correct. > I wasn't sure when reading what we currently have whether > it provided the 8-byte-aligned guarantee, rather than merely > the 4-byte-aligned one. I was trying to highlight the difference between SUBALIGN and IFALIGN, and perhaps didn't do adequate job of it. r~