From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44289) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bUqkO-000474-HU for qemu-devel@nongnu.org; Wed, 03 Aug 2016 03:37:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bUqkK-00048x-Be for qemu-devel@nongnu.org; Wed, 03 Aug 2016 03:37:48 -0400 Received: from greensocs.com ([193.104.36.180]:58561) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bUqkJ-00048b-Vu for qemu-devel@nongnu.org; Wed, 03 Aug 2016 03:37:44 -0400 From: KONRAD Frederic References: <1465835259-21449-1-git-send-email-fred.konrad@greensocs.com> <1465835259-21449-10-git-send-email-fred.konrad@greensocs.com> Message-ID: <056dd013-ea59-557b-3a23-cdd9ae9ca251@greensocs.com> Date: Wed, 3 Aug 2016 09:38:24 +0200 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [RFC PATCH 09/11] zynqmp_crf: add the clock mechanism List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Edgar Iglesias , Mark Burton , QEMU Developers , Alistair Francis Le 29/07/2016 =E0 15:51, Peter Maydell a =E9crit : > On 13 June 2016 at 17:27, wrote: >> From: KONRAD Frederic >> >> This adds the pll to the zynqmp_crf and the dp_video clock output. >> >> Signed-off-by: KONRAD Frederic >> --- >> hw/misc/xilinx_zynqmp_crf.c | 440 +++++++++++++++++++++++++++++++++++= +++++++++ >> 1 file changed, 440 insertions(+) >> >> diff --git a/hw/misc/xilinx_zynqmp_crf.c b/hw/misc/xilinx_zynqmp_crf.c >> index 4c670a0..2097534 100644 >> --- a/hw/misc/xilinx_zynqmp_crf.c >> +++ b/hw/misc/xilinx_zynqmp_crf.c >> @@ -30,6 +30,7 @@ >> #include "hw/register.h" >> #include "qemu/bitops.h" >> #include "qemu/log.h" >> +#include "qemu/qemu-clock.h" >> >> #ifndef XILINX_CRF_APB_ERR_DEBUG >> #define XILINX_CRF_APB_ERR_DEBUG 0 >> @@ -281,6 +282,38 @@ typedef struct CRF_APB { >> >> uint32_t regs[R_MAX]; >> RegisterInfo regs_info[R_MAX]; >> + >> + /* input clocks */ >> + qemu_clk pss_ref_clk; >> + qemu_clk video_clk; >> + qemu_clk pss_alt_ref_clk; >> + qemu_clk aux_refclk; >> + qemu_clk gt_crx_ref_clk; >> + >> + /* internal clocks */ >> + qemu_clk apll_clk; >> + qemu_clk dpll_clk; >> + qemu_clk vpll_clk; >> + >> + /* output clocks */ >> + qemu_clk acpu_clk; >> + qemu_clk dbg_trace; >> + qemu_clk dbg_fdp; >> + qemu_clk dp_video_ref; >> + qemu_clk dp_audio_ref; >> + qemu_clk dp_stc_ref; >> + qemu_clk ddr; >> + qemu_clk gpu_ref; >> + qemu_clk sata_ref; >> + qemu_clk pcie_ref; >> + qemu_clk gdma_ref; >> + qemu_clk dpdma_ref; >> + qemu_clk topsw_main; >> + qemu_clk topsw_lsbus; >> + qemu_clk dbg_tstmp; >> + qemu_clk apll_to_lpd; >> + qemu_clk dpll_to_lpd; >> + qemu_clk vpll_to_lpd; >> } CRF_APB; > > This looks a bit weird. Why are the input clocks and the output > clocks the same type? I was expecting that an output clock would > be "owned" by this device (and so a qemu_clk), whereas an input > clock would just be a reference to a clock owned by the device > on the other end of it. > Hi Peter, Yes this is a choice I had to make. Basically there is nothing different between what we call output and=20 input: They both allow to set a callback before the frequency is=20 transported to the next clock in the clock tree. And I use a name to get the clock, eg: for a simple clock divider: ---------------- in --o| ClockDivider |o-- out ---------------- will be modeled like this in terms of qemu_clock: freq_update_cb() return rate/4; | | \_/ ------------ ------------ --o| qemu_clk |o-- bindings --o| qemu_clk |o-- | in | | out | ------------ ------------ Then to bind that to a fixed clock we have in the machine model: qemu_clk_bind_clock( qemu_clk_get_pin(FixedClock, "out"), qemu_clk_get_pin(ClockDivider, "in")); Thanks, Fred > thanks > -- PMM >