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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id z16sm4996348pff.125.2020.02.11.10.55.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Feb 2020 10:55:18 -0800 (PST) Subject: Re: [PATCH 13/13] target/arm: Correct handling of PMCR_EL0.LC bit To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20200211173726.22541-1-peter.maydell@linaro.org> <20200211173726.22541-14-peter.maydell@linaro.org> From: Richard Henderson Message-ID: <059ac7e7-c4ca-7456-69f7-80c3cb2cbf09@linaro.org> Date: Tue, 11 Feb 2020 10:55:16 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200211173726.22541-14-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/11/20 9:37 AM, Peter Maydell wrote: > The LC bit in the PMCR_EL0 register is supposed to be: > * read/write > * RES1 on an AArch64-only implementation > * an architecturally UNKNOWN value on reset > (and use of LC==0 by software is deprecated). > > We were implementing it incorrectly as read-only always zero, > though we do have all the code needed to test it and behave > accordingly. > > Instead make it a read-write bit which resets to 1 always, which > satisfies all the architectural requirements above. > > Signed-off-by: Peter Maydell > --- > target/arm/helper.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson r~