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Thu, 01 Aug 2024 22:52:52 -0700 (PDT) Message-ID: <05d5a772-a7b9-4bfd-8ca0-f85dcf2d1505@linaro.org> Date: Fri, 2 Aug 2024 15:52:46 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] target/riscv: Relax fld alignment requirement To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com References: <20240802031612.604-1-zhiwei_liu@linux.alibaba.com> <20240802031612.604-4-zhiwei_liu@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240802031612.604-4-zhiwei_liu@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/2/24 13:16, LIU Zhiwei wrote: > According to the risc-v specification: > "FLD and FSD are only guaranteed to execute atomically if the effective > address is naturally aligned and XLEN≥64." > > We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does > not violate the rules. But it will hide some problems. So relax it to > MO_ATOM_NONE. > > Signed-off-by: LIU Zhiwei > --- > target/riscv/insn_trans/trans_rvd.c.inc | 26 ++++++++++++++++++------- > 1 file changed, 19 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc > index dbe508c7e0..458d7db745 100644 > --- a/target/riscv/insn_trans/trans_rvd.c.inc > +++ b/target/riscv/insn_trans/trans_rvd.c.inc > @@ -48,12 +48,20 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) > REQUIRE_EXT(ctx, RVD); > > /* > - * Zama16b applies to loads and stores of no more than MXLEN bits defined > - * in the F, D, and Q extensions. Otherwise, it falls through to default > - * MO_ATOM_IFALIGN. > + * FLD and FSD are only guaranteed to execute atomically if the effective > + * address is naturally aligned and XLEN≥64. > */ > - if ((ctx->misa_mxl_max >= MXL_RV64) && ctx->cfg_ptr->ext_zama16b) { > - memop |= MO_ATOM_WITHIN16; > + if (ctx->misa_mxl_max >= MXL_RV64) { > + /* > + * Zama16b applies to loads and stores of no more than MXLEN bits > + * defined in the F, D, and Q extensions. Otherwise, it falls through > + * to default MO_ATOM_IFALIGN. > + */ > + if (ctx->cfg_ptr->ext_zama16b) { > + memop |= MO_ATOM_WITHIN16; > + } > + } else { > + memop |= MO_ATOM_NONE; > } Does this really have byte atomicity, not atomic on two aligned 32-bit loads (which would be MO_ATOM_IFALIGN_PAIR). It's probably clearer to fill out the if-tree completely, rather than explain about defaults. if (get_mxl(ctx) == MXL_RV32) { memop |= MO_ATOM_NONE; } else if (ctx->cfg_ptr->ext_zama16b) { memop |= MO_ATOM_WITHIN16; } else { memop |= MO_ATOM_IFALIGN; } r~