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Mon, 08 May 2023 10:33:02 -0700 (PDT) Message-ID: <05e8478e-ebf9-c04d-3311-142cb6e11743@linaro.org> Date: Mon, 8 May 2023 18:32:55 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v4 48/57] tcg/ppc: Use atom_and_align_for_opc To: Peter Maydell Cc: qemu-devel@nongnu.org, git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org References: <20230503070656.1746170-1-richard.henderson@linaro.org> <20230503070656.1746170-49-richard.henderson@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1131; envelope-from=richard.henderson@linaro.org; helo=mail-yw1-x1131.google.com X-Spam_score_int: -38 X-Spam_score: -3.9 X-Spam_bar: --- X-Spam_report: (-3.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.802, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/5/23 14:18, Peter Maydell wrote: > On Wed, 3 May 2023 at 08:13, Richard Henderson > wrote: >> >> Signed-off-by: Richard Henderson >> --- >> tcg/ppc/tcg-target.c.inc | 17 ++++++++++++++++- >> 1 file changed, 16 insertions(+), 1 deletion(-) >> >> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc >> index f0a4118bbb..60375804cd 100644 >> --- a/tcg/ppc/tcg-target.c.inc >> +++ b/tcg/ppc/tcg-target.c.inc >> @@ -2034,7 +2034,22 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, >> { >> TCGLabelQemuLdst *ldst = NULL; >> MemOp opc = get_memop(oi); >> - unsigned a_bits = get_alignment_bits(opc); >> + MemOp a_bits, atom_a, atom_u; >> + >> + /* >> + * Book II, Section 1.4, Single-Copy Atomicity, specifies: >> + * >> + * Before 3.0, "An access that is not atomic is performed as a set of >> + * smaller disjoint atomic accesses. In general, the number and alignment >> + * of these accesses are implementation-dependent." Thus MO_ATOM_IFALIGN. >> + * >> + * As of 3.0, "the non-atomic access is performed as described in >> + * the corresponding list", which matches MO_ATOM_SUBALIGN. >> + */ >> + a_bits = atom_and_align_for_opc(s, &atom_a, &atom_u, opc, >> + have_isa_3_00 ? MO_ATOM_SUBALIGN >> + : MO_ATOM_IFALIGN, >> + false); >> > > Why doesn't this patch have changes to a HostAddress struct > like all the other archs ? Because the alignment as only required here, within prepare_host_addr. The Power LQ instruction allows unaligned input, unlike x86 VMOVDQA. r~