From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7HOG-0003PF-S8 for qemu-devel@nongnu.org; Mon, 30 May 2016 03:13:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b7HOC-0002Rx-Jr for qemu-devel@nongnu.org; Mon, 30 May 2016 03:13:31 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:54625) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7HOC-0002Rr-Cv for qemu-devel@nongnu.org; Mon, 30 May 2016 03:13:28 -0400 Received: from pova.uni-paderborn.de ([131.234.189.23] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.84_2 hoth) id 1b7HOB-00058i-S5 for qemu-devel@nongnu.org; Mon, 30 May 2016 09:13:27 +0200 Received: from mail.uni-paderborn.de by pova with queue id 1136189-2 for qemu-devel@nongnu.org; Mon, 30 May 2016 07:13:27 GMT References: <1464562768-8954-1-git-send-email-peer.adelt@c-lab.de> <1464562768-8954-4-git-send-email-peer.adelt@c-lab.de> From: Bastian Koppelmann Message-ID: <0614c12c-1360-484e-f376-971ad314c7aa@mail.uni-paderborn.de> Date: Mon, 30 May 2016 09:13:25 +0200 MIME-Version: 1.0 In-Reply-To: <1464562768-8954-4-git-send-email-peer.adelt@c-lab.de> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 3/4] target-tricore: Added new MOV instruction variant List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peer.adelt@c-lab.de, qemu-devel@nongnu.org On 05/30/2016 12:59 AM, peer.adelt@c-lab.de wrote: > From: Peer Adelt > > Puts the content of data register D[a] into E[c][63:32] and the > content of data register D[b] into E[c][31:0]. > > Signed-off-by: Peer Adelt > --- > target-tricore/translate.c | 4 ++++ > target-tricore/tricore-opcodes.h | 1 + > 2 files changed, 5 insertions(+) > > diff --git a/target-tricore/translate.c b/target-tricore/translate.c > index e66b433..2145f64 100644 > --- a/target-tricore/translate.c > +++ b/target-tricore/translate.c > @@ -6224,6 +6224,10 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) > case OPC2_32_RR_MOV: > tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); > break; > + case OPC2_32_RR_MOV_EXT: > + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); > + tcg_gen_mov_tl(cpu_gpr_d[(r3 + 1)], cpu_gpr_d[r2]); > + break; Since this is a 1.6+ instruction, please check the hflags for the 1.6 ISA and raise an exception if 1.6+ ISA is not met. See OPC1_16_SRC_MOV_E as an example. Cheers, Bastian