From: "Andreas Färber" <afaerber@suse.de>
To: Richard Henderson <rth@twiddle.net>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
peter.maydell@linaro.org, kbastian@mail.uni-paderborn.de
Subject: Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G)
Date: Mon, 26 Sep 2016 18:35:32 +0200 [thread overview]
Message-ID: <0699e3d0-06b2-6ee2-78ed-1d598a143c2b@suse.de> (raw)
In-Reply-To: <84c4e8a0-6f5b-cf09-8000-ffd677537ef8@redhat.com>
Am 26.09.2016 um 18:24 schrieb Paolo Bonzini:
> On 26/09/2016 18:20, Andreas Färber wrote:
>> Am 26.09.2016 um 18:17 schrieb Richard Henderson:
>>> On 09/26/2016 05:20 AM, Paolo Bonzini wrote:
>>>> On 26/09/2016 12:56, Sagar Karandikar wrote:
>>>>> -cpu-qom.h merged into cpu.h
>>>>
>>>> Please follow the model of other targets. RISCVCPUClass and the
>>>> RISCVCPU typedef should be in cpu-qom.h.
After discussion with Paolo, the key word here is typedef. It doesn't
make sense to have the struct RISCVCPU in cpu-qom.h (the old approach)
but it makes perfect sense to have struct RISCVCPUClass and typedef
RISCVCPU in a separate cpu-qom.h.
Sorry for misunderstanding,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
next prev parent reply other threads:[~2016-09-26 16:35 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-26 10:56 [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G) Sagar Karandikar
2016-09-26 10:56 ` [Qemu-devel] [PATCH 01/18] target-riscv: Add RISC-V target stubs and Maintainer Sagar Karandikar
2016-09-26 19:06 ` Eric Blake
2016-09-26 10:56 ` [Qemu-devel] [PATCH 02/18] target-riscv: Add RISC-V Target stubs inside target-riscv/ Sagar Karandikar
2016-09-26 16:30 ` Richard Henderson
2016-09-26 21:50 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 03/18] target-riscv: Add initialization for translation Sagar Karandikar
2016-09-26 16:34 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 04/18] target-riscv: Add framework for instruction decode Sagar Karandikar
2016-09-26 16:49 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 05/18] target-riscv: Add Arithmetic instructions Sagar Karandikar
2016-09-26 17:31 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 06/18] target-riscv: Add JALR, Branch Instructions Sagar Karandikar
2016-09-26 18:28 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 07/18] target-riscv: Add Loads/Stores, FP Loads/Stores Sagar Karandikar
2016-09-26 20:44 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 08/18] target-riscv: Add Atomic Instructions Sagar Karandikar
2016-09-27 19:30 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions, Sagar Karandikar
2016-09-26 21:15 ` Richard Henderson
2016-09-27 19:20 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 10/18] target-riscv: Add Single Precision Floating-Point Instructions Sagar Karandikar
2016-09-26 21:35 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 11/18] target-riscv: Add Double " Sagar Karandikar
2016-09-26 21:37 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 12/18] target-riscv: Add system instructions Sagar Karandikar
2016-09-26 12:21 ` Paolo Bonzini
2016-09-26 12:38 ` Bastian Koppelmann
2016-09-26 12:44 ` Paolo Bonzini
2016-09-27 18:12 ` Sagar Karandikar
2016-09-26 21:41 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 13/18] target-riscv: Add CSR read/write helpers Sagar Karandikar
2016-09-26 10:56 ` [Qemu-devel] [PATCH 14/18] target-riscv: softmmu/address translation support Sagar Karandikar
2016-09-26 22:04 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 15/18] target-riscv: Interrupt Handling Sagar Karandikar
2016-09-26 22:07 ` Richard Henderson
2016-09-26 10:56 ` [Qemu-devel] [PATCH 16/18] target-riscv: Timer Support Sagar Karandikar
2016-09-26 10:56 ` [Qemu-devel] [PATCH 17/18] target-riscv: Add support for Host-Target Interface (HTIF) Devices Sagar Karandikar
2016-09-26 10:56 ` [Qemu-devel] [PATCH 18/18] target-riscv: Add generic test board, activate target Sagar Karandikar
2016-09-26 12:20 ` [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G) Paolo Bonzini
2016-09-26 16:17 ` Richard Henderson
2016-09-26 16:20 ` Andreas Färber
2016-09-26 16:24 ` Paolo Bonzini
2016-09-26 16:35 ` Andreas Färber [this message]
2016-09-26 16:37 ` Paolo Bonzini
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