Re: [PATCH] target/hppa: mask upper iaoq bits when returning to narrow mode

[Richard Henderson <richard.henderson@linaro.org>]

On 4/1/24 10:56, Sven Schnelle wrote:
>> This seems to be caused by IIAOQ's containing the upper bits. With the
>> patch below i'm able to boot. Not sure whether it's correct though.
>>
>> diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c
>> index 58c13d3e61..f7c4cca8f1 100644
>> --- a/target/hppa/int_helper.c
>> +++ b/target/hppa/int_helper.c
>> @@ -123,8 +123,14 @@ void hppa_cpu_do_interrupt(CPUState *cs)
>>           env->cr[CR_IIASQ] = 0;
>>           env->cr_back[0] = 0;
>>       }
>> -    env->cr[CR_IIAOQ] = env->iaoq_f;
>> -    env->cr_back[1] = env->iaoq_b;
>> +    if (old_psw & PSW_W) {
>> +        env->cr[CR_IIAOQ] = env->iaoq_f;
>> +        env->cr_back[1] = env->iaoq_b;
>> +    } else {
>> +        env->cr[CR_IIAOQ] = (env->iaoq_f & 0xffffffff);
>> +        env->cr_back[1] = env->iaoq_b & 0xffffffff;
>> +    }
>> +
> 
> I guess the interesting question where should these bits get masked out
> - i would assume that this place is to late, and it should happen
> earlier in trans_be/when the iaoq value is copied. On the other hand
> you had one commit that removed the masking in copy_iaoq_entry()...

I would have said this masking should not happen at all.


r~