From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50647) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYA6w-0007PI-Gp for qemu-devel@nongnu.org; Wed, 27 Jun 2018 09:03:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYA6s-0000wO-E1 for qemu-devel@nongnu.org; Wed, 27 Jun 2018 09:03:50 -0400 Received: from 6.mo177.mail-out.ovh.net ([46.105.51.249]:44393) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fYA6s-0000vh-72 for qemu-devel@nongnu.org; Wed, 27 Jun 2018 09:03:46 -0400 Received: from player797.ha.ovh.net (unknown [10.109.122.9]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 82EFCB8020 for ; Wed, 27 Jun 2018 15:03:44 +0200 (CEST) References: <20180626135928.23950-1-clg@kaod.org> <20180627033321-mutt-send-email-mst@kernel.org> <1d70c0f9179990cd33d7c82c5190179e60ae4ce3.camel@kernel.crashing.org> <20180627072825.GH14434@umbus.fritz.box> <65c545f3-6279-62af-9bd8-2be93a3d7d18@kaod.org> <9f9a4454bec8e7009a02d544d7a98f6215bd1fa0.camel@kernel.crashing.org> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <06a913d3-d694-0be4-c04b-bc6c8c8c88c6@kaod.org> Date: Wed, 27 Jun 2018 15:03:28 +0200 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andrea Bolognani , Benjamin Herrenschmidt , David Gibson Cc: "Michael S. Tsirkin" , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Marcel Apfelbaum On 06/27/2018 12:40 PM, Andrea Bolognani wrote: > On Wed, 2018-06-27 at 18:41 +1000, Benjamin Herrenschmidt wrote: >> On Wed, 2018-06-27 at 09:46 +0200, C=C3=A9dric Le Goater wrote: >>> So the "IBM PHB3 PCIE Root Port" is already user createable. >>> >>> I can take a look at user createable PHB3s. I think this is OK from a= model >>> perspective. The object is rather standalone, it needs the machine fo= r=20 >>> the XICS fabric and a couple of ids, phb id and chip id. These can co= me >>> from the command line. >>> >>> We want at least one PHB3 per socket/chip though.=20 >> >> We don't want the user to specify the SCOM addresses though (for the >> MMIO windows we should get skiboot to assign them). >> >> If the user gets to specify a thing it would be which of the 3 or 4 HW >> PHBs of the chip it is, the SCOM addresses gets deduced. >=20 > For pSeries guests libvirt will either automatically create, or > allow users to configure manually, PHBs with something like >=20 > > > >=20 > which is ultimately converted to >=20 > -device spapr-pci-host-bridge,index=3D1,id=3Dpci.1 >=20 > Ideally the interface for PowerNV guests can be made to be similar > if not identical at the libvirt level, without having to add too > many hacks... It would certainly help a lot if the QEMU interface > for PowerNV PHBs didn't stray too far from the above. >=20 I think that we will need an extra attribute to specify the chip, but=20 only in the case of a multichip system, which is not the common scenario. So the 'index' attribute should work fine.=20 Thanks, C.=20