Re: [PATCH v4 3/5] target/riscv: Move misa_mxl_max to class

[Akihiko Odaki <akihiko.odaki@daynix.com>]

On 2023/10/18 15:50, LIU Zhiwei wrote:
> 
> On 2023/10/18 2:53, Akihiko Odaki wrote:
>> misa_mxl_max is common for all instances of a RISC-V CPU class so they
>> are better put into class.
>>
>> Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
>> ---
>>   target/riscv/cpu-qom.h     |   1 +
>>   target/riscv/cpu.h         |   3 +-
>>   hw/riscv/boot.c            |   2 +-
>>   target/riscv/cpu.c         | 118 +++++++++++++++++++------------------
>>   target/riscv/gdbstub.c     |  12 ++--
>>   target/riscv/kvm/kvm-cpu.c |  10 ++--
>>   target/riscv/machine.c     |   7 +--
>>   target/riscv/tcg/tcg-cpu.c |  12 ++--
>>   target/riscv/translate.c   |   3 +-
>>   9 files changed, 88 insertions(+), 80 deletions(-)
>>
>> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
>> index f3fbe37a2c..33b6d52c90 100644
>> --- a/target/riscv/cpu-qom.h
>> +++ b/target/riscv/cpu-qom.h
>> @@ -68,5 +68,6 @@ struct RISCVCPUClass {
>>       /*< public >*/
>>       DeviceRealize parent_realize;
>>       ResettablePhases parent_phases;
>> +    uint32_t misa_mxl_max;  /* max mxl for this cpu */
>>   };
>>   #endif /* RISCV_CPU_QOM_H */
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index f8ffa5ee38..ef10efd1e7 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -159,7 +159,6 @@ struct CPUArchState {
>>       /* RISCVMXL, but uint32_t for vmstate migration */
>>       uint32_t misa_mxl;      /* current mxl */
>> -    uint32_t misa_mxl_max;  /* max mxl for this cpu */
>>       uint32_t misa_ext;      /* current extensions */
>>       uint32_t misa_ext_mask; /* max ext for this cpu */
>>       uint32_t xl;            /* current xlen */
>> @@ -711,7 +710,7 @@ enum riscv_pmu_event_idx {
>>   /* used by tcg/tcg-cpu.c*/
>>   void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool 
>> en);
>>   bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
>> -void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
>> +void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext);
>>   typedef struct RISCVCPUMultiExtConfig {
>>       const char *name;
>> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
>> index 52bf8e67de..b7cf08f479 100644
>> --- a/hw/riscv/boot.c
>> +++ b/hw/riscv/boot.c
>> @@ -36,7 +36,7 @@
>>   bool riscv_is_32bit(RISCVHartArrayState *harts)
>>   {
>> -    return harts->harts[0].env.misa_mxl_max == MXL_RV32;
>> +    return RISCV_CPU_GET_CLASS(&harts->harts[0])->misa_mxl_max == 
>> MXL_RV32;
> 
> Hi Akihiko,
> 
> Can we use the cached CPUClass  in CPUState?  Like
> 
> (RISCVCPUClass *)((CPUState *)(&harts->harts[0])->cc)

If just casting, you can do:
(RISCVCPUClass *)((Object *)&harts->harts[0])->class

But it removes type safety checks RISCV_CPU_GET_CLASS() provides. This 
is not a hot path so it's better to keep the checks.