From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@opensource.wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
alistair23@gmail.com
Subject: Re: [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction
Date: Fri, 3 Sep 2021 19:04:37 +0200 [thread overview]
Message-ID: <071cf027-72f9-756f-36af-758f35bb4123@linaro.org> (raw)
In-Reply-To: <289f8d59cf883fec5764cb0cea8da4430b6fd6da.1630624983.git.alistair.francis@wdc.com>
On 9/3/21 1:23 AM, Alistair Francis wrote:
> + target_ulong bins;
Surely uint32_t, at least until 64-bit insn width is required.
> + TCGv tmp = temp_new(ctx);
> +
> + tcg_gen_movi_tl(tmp, ctx->opcode);
> + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, bins));
tcg_gen_st_i32(tcg_constant_i32(ctx->opcode),
cpu_env, offsetof(CPURISCVState, bins));
r~
next prev parent reply other threads:[~2021-09-03 17:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-02 23:23 [PATCH v1 0/2] RISC-V: Populate mtval and stval Alistair Francis
2021-09-02 23:23 ` [PATCH v1 1/2] target/riscv: Implement the stval/mtval illegal instruction Alistair Francis
2021-09-03 17:04 ` Richard Henderson [this message]
2021-09-04 13:41 ` Bin Meng
2021-09-02 23:23 ` [PATCH v1 2/2] target/riscv: Set mtval and stval support Alistair Francis
2021-09-03 17:05 ` Richard Henderson
2021-09-03 23:58 ` Bin Meng
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