* [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support VBootRom
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-09-02 6:01 ` [SPAM] " Cédric Le Goater
2025-07-17 3:40 ` [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve Jamin Lin via
` (20 subsequent siblings)
21 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
Introduces support for loading a vbootrom image into the dedicated vbootrom
memory region in the AST2700 Full Core machine.
Additionally, it implements a mechanism to extract the content of fmc_cs0
flash data(backend file) and copy it into the memory-mapped region
corresponding to ASPEED_DEV_SPI_BOOT.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0-fc.c | 75 ++++++++++++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 7087be4288..e2eee6183f 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -11,6 +11,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
+#include "qemu/datadir.h"
#include "qapi/error.h"
#include "system/block-backend.h"
#include "system/system.h"
@@ -35,6 +36,7 @@ struct Ast2700FCState {
MemoryRegion ca35_memory;
MemoryRegion ca35_dram;
+ MemoryRegion ca35_boot_rom;
MemoryRegion ssp_memory;
MemoryRegion tsp_memory;
@@ -55,12 +57,65 @@ struct Ast2700FCState {
#define AST2700FC_HW_STRAP2 0x00000003
#define AST2700FC_FMC_MODEL "w25q01jvq"
#define AST2700FC_SPI_MODEL "w25q512jv"
+#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
+
+static void ast2700fc_ca35_load_vbootrom(AspeedSoCState *soc,
+ const char *bios_name, Error **errp)
+{
+ g_autofree char *filename = NULL;
+ int ret;
+
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+ if (!filename) {
+ error_setg(errp, "Could not find vbootrom image '%s'", bios_name);
+ return;
+ }
+
+ ret = load_image_mr(filename, &soc->vbootrom);
+ if (ret < 0) {
+ error_setg(errp, "Failed to load vbootrom image '%s'", bios_name);
+ return;
+ }
+}
+
+static void ast2700fc_ca35_write_boot_rom(DriveInfo *dinfo, hwaddr addr,
+ size_t rom_size, Error **errp)
+{
+ BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
+ g_autofree void *storage = NULL;
+ int64_t size;
+
+ /*
+ * The block backend size should have already been 'validated' by
+ * the creation of the m25p80 object.
+ */
+ size = blk_getlength(blk);
+ if (size <= 0) {
+ error_setg(errp, "failed to get flash size");
+ return;
+ }
+
+ if (rom_size > size) {
+ rom_size = size;
+ }
+
+ storage = g_malloc0(rom_size);
+ if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
+ error_setg(errp, "failed to read the initial flash content");
+ return;
+ }
+
+ rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
+}
static void ast2700fc_ca35_init(MachineState *machine)
{
Ast2700FCState *s = AST2700A1FC(machine);
+ const char *bios_name = NULL;
AspeedSoCState *soc;
AspeedSoCClass *sc;
+ uint64_t rom_size;
+ DriveInfo *mtd0;
object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1");
soc = ASPEED_SOC(&s->ca35);
@@ -118,6 +173,26 @@ static void ast2700fc_ca35_init(MachineState *machine)
ast2700fc_board_info.ram_size = machine->ram_size;
ast2700fc_board_info.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
+ /* Install first FMC flash content as a boot rom. */
+ if (!s->mmio_exec) {
+ mtd0 = drive_get(IF_MTD, 0, 0);
+
+ if (mtd0) {
+ rom_size = memory_region_size(&soc->spi_boot);
+ memory_region_init_rom(&s->ca35_boot_rom, NULL, "aspeed.boot_rom",
+ rom_size, &error_abort);
+ memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
+ &s->ca35_boot_rom, 1);
+ ast2700fc_ca35_write_boot_rom(mtd0,
+ sc->memmap[ASPEED_DEV_SPI_BOOT],
+ rom_size, &error_abort);
+ }
+ }
+
+ /* VBOOTROM */
+ bios_name = machine->firmware ?: VBOOTROM_FILE_NAME;
+ ast2700fc_ca35_load_vbootrom(soc, bios_name, &error_abort);
+
arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support VBootRom
2025-07-17 3:40 ` [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support VBootRom Jamin Lin via
@ 2025-09-02 6:01 ` Cédric Le Goater
2025-09-02 8:28 ` Jamin Lin
0 siblings, 1 reply; 61+ messages in thread
From: Cédric Le Goater @ 2025-09-02 6:01 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 7/17/25 05:40, Jamin Lin wrote:
> Introduces support for loading a vbootrom image into the dedicated vbootrom
> memory region in the AST2700 Full Core machine.
>
> Additionally, it implements a mechanism to extract the content of fmc_cs0
> flash data(backend file) and copy it into the memory-mapped region
> corresponding to ASPEED_DEV_SPI_BOOT.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> hw/arm/aspeed_ast27x0-fc.c | 75 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 75 insertions(+)
>
> diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
> index 7087be4288..e2eee6183f 100644
> --- a/hw/arm/aspeed_ast27x0-fc.c
> +++ b/hw/arm/aspeed_ast27x0-fc.c
> @@ -11,6 +11,7 @@
>
> #include "qemu/osdep.h"
> #include "qemu/units.h"
> +#include "qemu/datadir.h"
> #include "qapi/error.h"
> #include "system/block-backend.h"
> #include "system/system.h"
> @@ -35,6 +36,7 @@ struct Ast2700FCState {
>
> MemoryRegion ca35_memory;
> MemoryRegion ca35_dram;
> + MemoryRegion ca35_boot_rom;
> MemoryRegion ssp_memory;
> MemoryRegion tsp_memory;
>
> @@ -55,12 +57,65 @@ struct Ast2700FCState {
> #define AST2700FC_HW_STRAP2 0x00000003
> #define AST2700FC_FMC_MODEL "w25q01jvq"
> #define AST2700FC_SPI_MODEL "w25q512jv"
> +#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
> +
> +static void ast2700fc_ca35_load_vbootrom(AspeedSoCState *soc,
> + const char *bios_name, Error **errp)
> +{
> + g_autofree char *filename = NULL;
> + int ret;
> +
> + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
> + if (!filename) {
> + error_setg(errp, "Could not find vbootrom image '%s'", bios_name);
> + return;
> + }
> +
> + ret = load_image_mr(filename, &soc->vbootrom);
> + if (ret < 0) {
> + error_setg(errp, "Failed to load vbootrom image '%s'", bios_name);
> + return;
> + }
> +}
> +
> +static void ast2700fc_ca35_write_boot_rom(DriveInfo *dinfo, hwaddr addr,
> + size_t rom_size, Error **errp)
> +{
> + BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
> + g_autofree void *storage = NULL;
> + int64_t size;
> +
> + /*
> + * The block backend size should have already been 'validated' by
> + * the creation of the m25p80 object.
> + */
> + size = blk_getlength(blk);
> + if (size <= 0) {
> + error_setg(errp, "failed to get flash size");
> + return;
> + }
> +
> + if (rom_size > size) {
> + rom_size = size;
> + }
> +
> + storage = g_malloc0(rom_size);
> + if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
> + error_setg(errp, "failed to read the initial flash content");
> + return;
> + }
> +
> + rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
> +}
The above is duplicated code. Could we try to have common routines instead ?
> static void ast2700fc_ca35_init(MachineState *machine)
> {
> Ast2700FCState *s = AST2700A1FC(machine);
> + const char *bios_name = NULL;
> AspeedSoCState *soc;
> AspeedSoCClass *sc;
> + uint64_t rom_size;
> + DriveInfo *mtd0;
>
> object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1");
> soc = ASPEED_SOC(&s->ca35);
> @@ -118,6 +173,26 @@ static void ast2700fc_ca35_init(MachineState *machine)
> ast2700fc_board_info.ram_size = machine->ram_size;
> ast2700fc_board_info.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
>
> + /* Install first FMC flash content as a boot rom. */
This is a first addition for the ast2700fc machine and ...
> + if (!s->mmio_exec) {
> + mtd0 = drive_get(IF_MTD, 0, 0);
> +
> + if (mtd0) {
> + rom_size = memory_region_size(&soc->spi_boot);
> + memory_region_init_rom(&s->ca35_boot_rom, NULL, "aspeed.boot_rom",
> + rom_size, &error_abort);
> + memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
> + &s->ca35_boot_rom, 1);
> + ast2700fc_ca35_write_boot_rom(mtd0,
> + sc->memmap[ASPEED_DEV_SPI_BOOT],
> + rom_size, &error_abort);
> + }
> + }
> +
> + /* VBOOTROM */
... this is a second. Could you please split the changes ?
Thanks,
C.
> + bios_name = machine->firmware ?: VBOOTROM_FILE_NAME;
> + ast2700fc_ca35_load_vbootrom(soc, bios_name, &error_abort);
> +
> arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
> }
>
^ permalink raw reply [flat|nested] 61+ messages in thread* RE: [SPAM] [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support VBootRom
2025-09-02 6:01 ` [SPAM] " Cédric Le Goater
@ 2025-09-02 8:28 ` Jamin Lin
2025-09-02 13:23 ` Cédric Le Goater
0 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin @ 2025-09-02 8:28 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric
> Subject: Re: [SPAM] [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support
> VBootRom
>
> On 7/17/25 05:40, Jamin Lin wrote:
> > Introduces support for loading a vbootrom image into the dedicated
> > vbootrom memory region in the AST2700 Full Core machine.
> >
> > Additionally, it implements a mechanism to extract the content of
> > fmc_cs0 flash data(backend file) and copy it into the memory-mapped
> > region corresponding to ASPEED_DEV_SPI_BOOT.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > hw/arm/aspeed_ast27x0-fc.c | 75
> ++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 75 insertions(+)
> >
> > diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
> > index 7087be4288..e2eee6183f 100644
> > --- a/hw/arm/aspeed_ast27x0-fc.c
> > +++ b/hw/arm/aspeed_ast27x0-fc.c
> > @@ -11,6 +11,7 @@
> >
> > #include "qemu/osdep.h"
> > #include "qemu/units.h"
> > +#include "qemu/datadir.h"
> > #include "qapi/error.h"
> > #include "system/block-backend.h"
> > #include "system/system.h"
> > @@ -35,6 +36,7 @@ struct Ast2700FCState {
> >
> > MemoryRegion ca35_memory;
> > MemoryRegion ca35_dram;
> > + MemoryRegion ca35_boot_rom;
> > MemoryRegion ssp_memory;
> > MemoryRegion tsp_memory;
> >
> > @@ -55,12 +57,65 @@ struct Ast2700FCState {
> > #define AST2700FC_HW_STRAP2 0x00000003
> > #define AST2700FC_FMC_MODEL "w25q01jvq"
> > #define AST2700FC_SPI_MODEL "w25q512jv"
> > +#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
> > +
> > +static void ast2700fc_ca35_load_vbootrom(AspeedSoCState *soc,
> > + const char *bios_name,
> Error
> > +**errp) {
> > + g_autofree char *filename = NULL;
> > + int ret;
> > +
> > + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
> > + if (!filename) {
> > + error_setg(errp, "Could not find vbootrom image '%s'",
> bios_name);
> > + return;
> > + }
> > +
> > + ret = load_image_mr(filename, &soc->vbootrom);
> > + if (ret < 0) {
> > + error_setg(errp, "Failed to load vbootrom image '%s'",
> bios_name);
> > + return;
> > + }
> > +}
> > +
> > +static void ast2700fc_ca35_write_boot_rom(DriveInfo *dinfo, hwaddr addr,
> > + size_t rom_size, Error
> > +**errp) {
> > + BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
> > + g_autofree void *storage = NULL;
> > + int64_t size;
> > +
> > + /*
> > + * The block backend size should have already been 'validated' by
> > + * the creation of the m25p80 object.
> > + */
> > + size = blk_getlength(blk);
> > + if (size <= 0) {
> > + error_setg(errp, "failed to get flash size");
> > + return;
> > + }
> > +
> > + if (rom_size > size) {
> > + rom_size = size;
> > + }
> > +
> > + storage = g_malloc0(rom_size);
> > + if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
> > + error_setg(errp, "failed to read the initial flash content");
> > + return;
> > + }
> > +
> > + rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); }
>
> The above is duplicated code. Could we try to have common routines instead ?
Thanks for your review and suggestion.
Per our earlier discussion, we plan to refactor hw/arm/aspeed.c. As a first
step, I can move the vbootrom helpers into a common source file so they can be
reused by other boards.
Do you have a preference for the filename?
hw/arm/aspeed_utils.c (with a small header in include/hw/arm/aspeed_utils.h),
Once that’s in place, aspeed_ast27x0f.c can reuse these helpers to support
vbootrom with coprocessors.
Thanks-Jamin
#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
static void aspeed_load_vbootrom(AspeedMachineState *bmc, const char *bios_name,
Error **errp)
static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
uint64_t rom_size)
static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
Error **errp)
>
> > static void ast2700fc_ca35_init(MachineState *machine)
> > {
> > Ast2700FCState *s = AST2700A1FC(machine);
> > + const char *bios_name = NULL;
> > AspeedSoCState *soc;
> > AspeedSoCClass *sc;
> > + uint64_t rom_size;
> > + DriveInfo *mtd0;
> >
> > object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1");
> > soc = ASPEED_SOC(&s->ca35);
> > @@ -118,6 +173,26 @@ static void ast2700fc_ca35_init(MachineState
> *machine)
> > ast2700fc_board_info.ram_size = machine->ram_size;
> > ast2700fc_board_info.loader_start =
> > sc->memmap[ASPEED_DEV_SDRAM];
> >
> > + /* Install first FMC flash content as a boot rom. */
>
> This is a first addition for the ast2700fc machine and ...
>
> > + if (!s->mmio_exec) {
> > + mtd0 = drive_get(IF_MTD, 0, 0);
> > +
> > + if (mtd0) {
> > + rom_size = memory_region_size(&soc->spi_boot);
> > + memory_region_init_rom(&s->ca35_boot_rom, NULL,
> "aspeed.boot_rom",
> > + rom_size, &error_abort);
> > +
> memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
> > +
> &s->ca35_boot_rom, 1);
> > + ast2700fc_ca35_write_boot_rom(mtd0,
> > +
> sc->memmap[ASPEED_DEV_SPI_BOOT],
> > + rom_size,
> &error_abort);
> > + }
> > + }
> > +
> > + /* VBOOTROM */
>
> ... this is a second. Could you please split the changes ?
>
Will do
>
> Thanks,
>
> C.
>
>
>
>
> > + bios_name = machine->firmware ?: VBOOTROM_FILE_NAME;
> > + ast2700fc_ca35_load_vbootrom(soc, bios_name, &error_abort);
> > +
> > arm_load_kernel(ARM_CPU(first_cpu), machine,
> &ast2700fc_board_info);
> > }
> >
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support VBootRom
2025-09-02 8:28 ` Jamin Lin
@ 2025-09-02 13:23 ` Cédric Le Goater
2025-09-03 5:19 ` Jamin Lin
0 siblings, 1 reply; 61+ messages in thread
From: Cédric Le Goater @ 2025-09-02 13:23 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
On 9/2/25 10:28, Jamin Lin wrote:
> Hi Cédric
>
>> Subject: Re: [SPAM] [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support
>> VBootRom
>>
>> On 7/17/25 05:40, Jamin Lin wrote:
>>> Introduces support for loading a vbootrom image into the dedicated
>>> vbootrom memory region in the AST2700 Full Core machine.
>>>
>>> Additionally, it implements a mechanism to extract the content of
>>> fmc_cs0 flash data(backend file) and copy it into the memory-mapped
>>> region corresponding to ASPEED_DEV_SPI_BOOT.
>>>
>>> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
>>> ---
>>> hw/arm/aspeed_ast27x0-fc.c | 75
>> ++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 75 insertions(+)
>>>
>>> diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
>>> index 7087be4288..e2eee6183f 100644
>>> --- a/hw/arm/aspeed_ast27x0-fc.c
>>> +++ b/hw/arm/aspeed_ast27x0-fc.c
>>> @@ -11,6 +11,7 @@
>>>
>>> #include "qemu/osdep.h"
>>> #include "qemu/units.h"
>>> +#include "qemu/datadir.h"
>>> #include "qapi/error.h"
>>> #include "system/block-backend.h"
>>> #include "system/system.h"
>>> @@ -35,6 +36,7 @@ struct Ast2700FCState {
>>>
>>> MemoryRegion ca35_memory;
>>> MemoryRegion ca35_dram;
>>> + MemoryRegion ca35_boot_rom;
>>> MemoryRegion ssp_memory;
>>> MemoryRegion tsp_memory;
>>>
>>> @@ -55,12 +57,65 @@ struct Ast2700FCState {
>>> #define AST2700FC_HW_STRAP2 0x00000003
>>> #define AST2700FC_FMC_MODEL "w25q01jvq"
>>> #define AST2700FC_SPI_MODEL "w25q512jv"
>>> +#define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
>>> +
>>> +static void ast2700fc_ca35_load_vbootrom(AspeedSoCState *soc,
>>> + const char *bios_name,
>> Error
>>> +**errp) {
>>> + g_autofree char *filename = NULL;
>>> + int ret;
>>> +
>>> + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
>>> + if (!filename) {
>>> + error_setg(errp, "Could not find vbootrom image '%s'",
>> bios_name);
>>> + return;
>>> + }
>>> +
>>> + ret = load_image_mr(filename, &soc->vbootrom);
>>> + if (ret < 0) {
>>> + error_setg(errp, "Failed to load vbootrom image '%s'",
>> bios_name);
>>> + return;
>>> + }
>>> +}
>>> +
>>> +static void ast2700fc_ca35_write_boot_rom(DriveInfo *dinfo, hwaddr addr,
>>> + size_t rom_size, Error
>>> +**errp) {
>>> + BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
>>> + g_autofree void *storage = NULL;
>>> + int64_t size;
>>> +
>>> + /*
>>> + * The block backend size should have already been 'validated' by
>>> + * the creation of the m25p80 object.
>>> + */
>>> + size = blk_getlength(blk);
>>> + if (size <= 0) {
>>> + error_setg(errp, "failed to get flash size");
>>> + return;
>>> + }
>>> +
>>> + if (rom_size > size) {
>>> + rom_size = size;
>>> + }
>>> +
>>> + storage = g_malloc0(rom_size);
>>> + if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
>>> + error_setg(errp, "failed to read the initial flash content");
>>> + return;
>>> + }
>>> +
>>> + rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); }
>>
>> The above is duplicated code. Could we try to have common routines instead ?
>
> Thanks for your review and suggestion.
>
> Per our earlier discussion, we plan to refactor hw/arm/aspeed.c. As a first
> step, I can move the vbootrom helpers into a common source file so they can be
> reused by other boards.
>
> Do you have a preference for the filename?
> hw/arm/aspeed_utils.c (with a small header in include/hw/arm/aspeed_utils.h),
There is a aspeed_soc_common.c file for such helpers.
Thanks,
C.
^ permalink raw reply [flat|nested] 61+ messages in thread* RE: [SPAM] [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support VBootRom
2025-09-02 13:23 ` Cédric Le Goater
@ 2025-09-03 5:19 ` Jamin Lin
2025-09-03 8:48 ` Jamin Lin
0 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin @ 2025-09-03 5:19 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric,
> Subject: Re: [SPAM] [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support
> VBootRom
>
> On 9/2/25 10:28, Jamin Lin wrote:
> > Hi Cédric
> >
> >> Subject: Re: [SPAM] [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc:
> >> Support VBootRom
> >>
> >
> > Thanks for your review and suggestion.
> >
> > Per our earlier discussion, we plan to refactor hw/arm/aspeed.c. As a
> > first step, I can move the vbootrom helpers into a common source file
> > so they can be reused by other boards.
> >
> > Do you have a preference for the filename?
> > hw/arm/aspeed_utils.c (with a small header in
> > include/hw/arm/aspeed_utils.h),
>
>
> There is a aspeed_soc_common.c file for such helpers.
>
Thanks for the suggestions.
It seems that aspeed_soc_common.c is meant for code shared across all ASPEED SoCs rather than the board-specific code.
I am planning to move the following APIs into a common file.
static void aspeed_load_vbootrom(AspeedMachineState *bmc, const char *bios_name,
Error **errp)
static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
uint64_t rom_size)
static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
Error **errp)
To build successfully, the AspeedMachineState struct also needs to be moved into aspeed.h.
struct AspeedMachineState {
/* Private */
MachineState parent_obj;
/* Public */
AspeedSoCState *soc;
MemoryRegion boot_rom;
bool mmio_exec;
uint32_t uart_chosen;
char *fmc_model;
char *spi_model;
uint32_t hw_strap1;
};
If I place the above APIs in aspeed_soc_common.h that header would also need to include aspeed.h.
To avoid mixing SOC-level and board-level code, I propose creating a new c/h file to place them such
as aspeed_board_common.c and aspeed_board_common.h
Do you have any concerns or could you please give me any suggestion?
Thanks-Jamin
>
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 61+ messages in thread* RE: [SPAM] [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support VBootRom
2025-09-03 5:19 ` Jamin Lin
@ 2025-09-03 8:48 ` Jamin Lin
0 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin @ 2025-09-03 8:48 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric
> Subject: RE: [SPAM] [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support
> VBootRom
>
> Hi Cédric,
>
> > Subject: Re: [SPAM] [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support
> > VBootRom
> >
> > On 9/2/25 10:28, Jamin Lin wrote:
> > > Hi Cédric
> > >
> > >> Subject: Re: [SPAM] [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc:
> > >> Support VBootRom
> > >>
> > >
> > > Thanks for your review and suggestion.
> > >
> > > Per our earlier discussion, we plan to refactor hw/arm/aspeed.c. As
> > > a first step, I can move the vbootrom helpers into a common source
> > > file so they can be reused by other boards.
> > >
> > > Do you have a preference for the filename?
> > > hw/arm/aspeed_utils.c (with a small header in
> > > include/hw/arm/aspeed_utils.h),
> >
> >
> > There is a aspeed_soc_common.c file for such helpers.
> >
> Thanks for the suggestions.
>
Sorry, please ignore my previous comments.
I realized that I can replace AspeedMachineState with AspeedSoCState to make the API more generic.
Apologies for the inconvenience.
Jamin
> It seems that aspeed_soc_common.c is meant for code shared across all
> ASPEED SoCs rather than the board-specific code.
> I am planning to move the following APIs into a common file.
>
> static void aspeed_load_vbootrom(AspeedMachineState *bmc, const char
> *bios_name,
> Error **errp) static void
> aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
> uint64_t rom_size) static void
> write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
> Error **errp)
>
> To build successfully, the AspeedMachineState struct also needs to be moved
> into aspeed.h.
>
> struct AspeedMachineState {
> /* Private */
> MachineState parent_obj;
> /* Public */
>
> AspeedSoCState *soc;
> MemoryRegion boot_rom;
> bool mmio_exec;
> uint32_t uart_chosen;
> char *fmc_model;
> char *spi_model;
> uint32_t hw_strap1;
> };
>
> If I place the above APIs in aspeed_soc_common.h that header would also
> need to include aspeed.h.
> To avoid mixing SOC-level and board-level code, I propose creating a new c/h
> file to place them such as aspeed_board_common.c and
> aspeed_board_common.h Do you have any concerns or could you please give
> me any suggestion?
>
> Thanks-Jamin
>
> >
> > Thanks,
> >
> > C.
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support VBootRom Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-09-02 6:20 ` [SPAM] " Cédric Le Goater
2025-07-17 3:40 ` [PATCH v1 03/21] hw/arm/ast27x0: Move TSP " Jamin Lin via
` (19 subsequent siblings)
21 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
In the previous design, the SSP coprocessor (aspeed27x0ssp-soc) was initialized
and realized at the machine level (e.g., AST2700FC). However, to make sure the
coprocessors can work together properly—such as using the same SRAM, sharing
the SCU, and having consistent memory remapping—we need to change how these
devices are set up.
This commit moves the SSP coprocessor initialization and realization into the
AST2700 SoC (aspeed_soc_ast2700_init() and aspeed_soc_ast2700_realize()).
By doing so, the SSP becomes a proper child of the SoC device, rather than
the machine.
This is a preparation step for future commits that will support shared SCU,
SRAM, and memory remap logic—specifically enabling PSP DRAM remap for SSP SDRAM
access.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 27 +++++++++++++-----------
hw/arm/aspeed_ast27x0-fc.c | 30 ++------------------------
hw/arm/aspeed_ast27x0.c | 42 +++++++++++++++++++++++++++++++++++++
3 files changed, 59 insertions(+), 40 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 217ef0eafd..2831da91ab 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -128,6 +128,19 @@ struct Aspeed2600SoCState {
#define TYPE_ASPEED2600_SOC "aspeed2600-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
+struct Aspeed27x0SSPSoCState {
+ AspeedSoCState parent;
+ AspeedINTCState intc[2];
+ UnimplementedDeviceState ipc[2];
+ UnimplementedDeviceState scuio;
+ MemoryRegion memory;
+
+ ARMv7MState armv7m;
+};
+
+#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
+
struct Aspeed27x0SoCState {
AspeedSoCState parent;
@@ -135,6 +148,8 @@ struct Aspeed27x0SoCState {
AspeedINTCState intc[2];
GICv3State gic;
MemoryRegion dram_empty;
+
+ Aspeed27x0SSPSoCState ssp;
};
#define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
@@ -146,18 +161,6 @@ struct Aspeed10x0SoCState {
ARMv7MState armv7m;
};
-struct Aspeed27x0SSPSoCState {
- AspeedSoCState parent;
- AspeedINTCState intc[2];
- UnimplementedDeviceState ipc[2];
- UnimplementedDeviceState scuio;
-
- ARMv7MState armv7m;
-};
-
-#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
-OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
-
struct Aspeed27x0TSPSoCState {
AspeedSoCState parent;
AspeedINTCState intc[2];
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index e2eee6183f..c9b338fe78 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -37,14 +37,11 @@ struct Ast2700FCState {
MemoryRegion ca35_memory;
MemoryRegion ca35_dram;
MemoryRegion ca35_boot_rom;
- MemoryRegion ssp_memory;
MemoryRegion tsp_memory;
- Clock *ssp_sysclk;
Clock *tsp_sysclk;
Aspeed27x0SoCState ca35;
- Aspeed27x0SSPSoCState ssp;
Aspeed27x0TSPSoCState tsp;
bool mmio_exec;
@@ -158,6 +155,8 @@ static void ast2700fc_ca35_init(MachineState *machine)
return;
}
aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0));
+ aspeed_soc_uart_set_chr(ASPEED_SOC(&s->ca35.ssp), ASPEED_DEV_UART4,
+ serial_hd(1));
if (!qdev_realize(DEVICE(&s->ca35), NULL, &error_abort)) {
return;
}
@@ -196,30 +195,6 @@ static void ast2700fc_ca35_init(MachineState *machine)
arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
}
-static void ast2700fc_ssp_init(MachineState *machine)
-{
- AspeedSoCState *soc;
- Ast2700FCState *s = AST2700A1FC(machine);
- s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
- clock_set_hz(s->ssp_sysclk, 200000000ULL);
-
- object_initialize_child(OBJECT(s), "ssp", &s->ssp, TYPE_ASPEED27X0SSP_SOC);
- memory_region_init(&s->ssp_memory, OBJECT(&s->ssp), "ssp-memory",
- UINT64_MAX);
-
- qdev_connect_clock_in(DEVICE(&s->ssp), "sysclk", s->ssp_sysclk);
- if (!object_property_set_link(OBJECT(&s->ssp), "memory",
- OBJECT(&s->ssp_memory), &error_abort)) {
- return;
- }
-
- soc = ASPEED_SOC(&s->ssp);
- aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART4, serial_hd(1));
- if (!qdev_realize(DEVICE(&s->ssp), NULL, &error_abort)) {
- return;
- }
-}
-
static void ast2700fc_tsp_init(MachineState *machine)
{
AspeedSoCState *soc;
@@ -247,7 +222,6 @@ static void ast2700fc_tsp_init(MachineState *machine)
static void ast2700fc_init(MachineState *machine)
{
ast2700fc_ca35_init(machine);
- ast2700fc_ssp_init(machine);
ast2700fc_tsp_init(machine);
}
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 6aa3841b69..ffbc32fef2 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -22,6 +22,8 @@
#include "hw/intc/arm_gicv3.h"
#include "qobject/qlist.h"
#include "qemu/log.h"
+#include "hw/qdev-clock.h"
+#include "hw/boards.h"
#define AST2700_SOC_IO_SIZE 0x00FE0000
#define AST2700_SOC_IOMEM_SIZE 0x01000000
@@ -410,6 +412,8 @@ static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp)
static void aspeed_soc_ast2700_init(Object *obj)
{
+ MachineState *ms = MACHINE(qdev_get_machine());
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj);
AspeedSoCState *s = ASPEED_SOC(obj);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
@@ -426,6 +430,11 @@ static void aspeed_soc_ast2700_init(Object *obj)
aspeed_soc_cpu_type(sc));
}
+ /* Coprocessors */
+ if (mc->default_cpus > sc->num_cpus) {
+ object_initialize_child(obj, "ssp", &a->ssp, TYPE_ASPEED27X0SSP_SOC);
+ }
+
object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
@@ -610,9 +619,35 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
return true;
}
+static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
+{
+ Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
+ AspeedSoCState *s = ASPEED_SOC(dev);
+ Clock *sysclk;
+
+ sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
+ clock_set_hz(sysclk, 200000000ULL);
+ qdev_connect_clock_in(DEVICE(&a->ssp), "sysclk", sysclk);
+
+ memory_region_init(&a->ssp.memory, OBJECT(&a->ssp), "ssp-memory",
+ UINT64_MAX);
+ if (!object_property_set_link(OBJECT(&a->ssp), "memory",
+ OBJECT(&a->ssp.memory), &error_abort)) {
+ return false;
+ }
+
+ if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
+ return false;
+ }
+
+ return true;
+}
+
static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
{
int i;
+ MachineState *ms = MACHINE(qdev_get_machine());
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
@@ -719,6 +754,13 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
sc->memmap[ASPEED_DEV_SCUIO]);
+ /* Coprocessors */
+ if (mc->default_cpus > sc->num_cpus) {
+ if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
+ return;
+ }
+ }
+
/* UART */
if (!aspeed_soc_uart_realize(s, errp)) {
return;
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve
2025-07-17 3:40 ` [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve Jamin Lin via
@ 2025-09-02 6:20 ` Cédric Le Goater
2025-09-02 7:27 ` Markus Armbruster
2025-09-02 8:41 ` Jamin Lin
0 siblings, 2 replies; 61+ messages in thread
From: Cédric Le Goater @ 2025-09-02 6:20 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 7/17/25 05:40, Jamin Lin wrote:
> In the previous design, the SSP coprocessor (aspeed27x0ssp-soc) was initialized
> and realized at the machine level (e.g., AST2700FC). However, to make sure the
> coprocessors can work together properly—such as using the same SRAM, sharing
> the SCU, and having consistent memory remapping—we need to change how these
> devices are set up.
>
> This commit moves the SSP coprocessor initialization and realization into the
> AST2700 SoC (aspeed_soc_ast2700_init() and aspeed_soc_ast2700_realize()).
> By doing so, the SSP becomes a proper child of the SoC device, rather than
> the machine.
>
> This is a preparation step for future commits that will support shared SCU,
> SRAM, and memory remap logic—specifically enabling PSP DRAM remap for SSP SDRAM
> access.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> include/hw/arm/aspeed_soc.h | 27 +++++++++++++-----------
> hw/arm/aspeed_ast27x0-fc.c | 30 ++------------------------
> hw/arm/aspeed_ast27x0.c | 42 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 59 insertions(+), 40 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 217ef0eafd..2831da91ab 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -128,6 +128,19 @@ struct Aspeed2600SoCState {
> #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
> OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
>
> +struct Aspeed27x0SSPSoCState {
> + AspeedSoCState parent;
> + AspeedINTCState intc[2];
> + UnimplementedDeviceState ipc[2];
> + UnimplementedDeviceState scuio;
> + MemoryRegion memory;
> +
> + ARMv7MState armv7m;
> +};
> +
> +#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
> +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
> +
> struct Aspeed27x0SoCState {
> AspeedSoCState parent;
>
> @@ -135,6 +148,8 @@ struct Aspeed27x0SoCState {
> AspeedINTCState intc[2];
> GICv3State gic;
> MemoryRegion dram_empty;
> +
> + Aspeed27x0SSPSoCState ssp;
> };
>
> #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
> @@ -146,18 +161,6 @@ struct Aspeed10x0SoCState {
> ARMv7MState armv7m;
> };
>
> -struct Aspeed27x0SSPSoCState {
> - AspeedSoCState parent;
> - AspeedINTCState intc[2];
> - UnimplementedDeviceState ipc[2];
> - UnimplementedDeviceState scuio;
> -
> - ARMv7MState armv7m;
> -};
> -
> -#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
> -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
> -
> struct Aspeed27x0TSPSoCState {
> AspeedSoCState parent;
> AspeedINTCState intc[2];
> diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
> index e2eee6183f..c9b338fe78 100644
> --- a/hw/arm/aspeed_ast27x0-fc.c
> +++ b/hw/arm/aspeed_ast27x0-fc.c
> @@ -37,14 +37,11 @@ struct Ast2700FCState {
> MemoryRegion ca35_memory;
> MemoryRegion ca35_dram;
> MemoryRegion ca35_boot_rom;
> - MemoryRegion ssp_memory;
> MemoryRegion tsp_memory;
>
> - Clock *ssp_sysclk;
> Clock *tsp_sysclk;
>
> Aspeed27x0SoCState ca35;
> - Aspeed27x0SSPSoCState ssp;
> Aspeed27x0TSPSoCState tsp;
>
> bool mmio_exec;
> @@ -158,6 +155,8 @@ static void ast2700fc_ca35_init(MachineState *machine)
> return;
> }
> aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0));
> + aspeed_soc_uart_set_chr(ASPEED_SOC(&s->ca35.ssp), ASPEED_DEV_UART4,
> + serial_hd(1));
hmm, I wonder if the second uart shouldn't be set from the init handler
of the Aspeed27x0SSPSoCState child object.
> if (!qdev_realize(DEVICE(&s->ca35), NULL, &error_abort)) {
> return;
> }
> @@ -196,30 +195,6 @@ static void ast2700fc_ca35_init(MachineState *machine)
> arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
> }
>
> -static void ast2700fc_ssp_init(MachineState *machine)
> -{
> - AspeedSoCState *soc;
> - Ast2700FCState *s = AST2700A1FC(machine);
> - s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
> - clock_set_hz(s->ssp_sysclk, 200000000ULL);
> -
> - object_initialize_child(OBJECT(s), "ssp", &s->ssp, TYPE_ASPEED27X0SSP_SOC);
> - memory_region_init(&s->ssp_memory, OBJECT(&s->ssp), "ssp-memory",
> - UINT64_MAX);
> -
> - qdev_connect_clock_in(DEVICE(&s->ssp), "sysclk", s->ssp_sysclk);
> - if (!object_property_set_link(OBJECT(&s->ssp), "memory",
> - OBJECT(&s->ssp_memory), &error_abort)) {
> - return;
> - }
> -
> - soc = ASPEED_SOC(&s->ssp);
> - aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART4, serial_hd(1));
> - if (!qdev_realize(DEVICE(&s->ssp), NULL, &error_abort)) {
> - return;
> - }
> -}
> -
> static void ast2700fc_tsp_init(MachineState *machine)
> {
> AspeedSoCState *soc;
> @@ -247,7 +222,6 @@ static void ast2700fc_tsp_init(MachineState *machine)
> static void ast2700fc_init(MachineState *machine)
> {
> ast2700fc_ca35_init(machine);
> - ast2700fc_ssp_init(machine);
> ast2700fc_tsp_init(machine);
> }
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 6aa3841b69..ffbc32fef2 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -22,6 +22,8 @@
> #include "hw/intc/arm_gicv3.h"
> #include "qobject/qlist.h"
> #include "qemu/log.h"
> +#include "hw/qdev-clock.h"
> +#include "hw/boards.h"
>
> #define AST2700_SOC_IO_SIZE 0x00FE0000
> #define AST2700_SOC_IOMEM_SIZE 0x01000000
> @@ -410,6 +412,8 @@ static bool aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp)
>
> static void aspeed_soc_ast2700_init(Object *obj)
> {
> + MachineState *ms = MACHINE(qdev_get_machine());
Calling qdev_get_machine() in a device model is a no-no. Please don't.
> + MachineClass *mc = MACHINE_GET_CLASS(ms);
> Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj);
> AspeedSoCState *s = ASPEED_SOC(obj);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> @@ -426,6 +430,11 @@ static void aspeed_soc_ast2700_init(Object *obj)
> aspeed_soc_cpu_type(sc));
> }
>
> + /* Coprocessors */
> + if (mc->default_cpus > sc->num_cpus) {
That's a hack.
We need to find another way to conditionally create the co-processors
if that's what you want to do. A SoC class attribute would be a better
way.
> + object_initialize_child(obj, "ssp", &a->ssp, TYPE_ASPEED27X0SSP_SOC);
> + }
> +
> object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
>
> object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
> @@ -610,9 +619,35 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
> return true;
> }
>
> +static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
I would pass 'Aspeed27x0SoCState *' instead.
> +{
> + Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
> + AspeedSoCState *s = ASPEED_SOC(dev);
> + Clock *sysclk;
> +
> + sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
> + clock_set_hz(sysclk, 200000000ULL);
> + qdev_connect_clock_in(DEVICE(&a->ssp), "sysclk", sysclk);
> +
> + memory_region_init(&a->ssp.memory, OBJECT(&a->ssp), "ssp-memory",
> + UINT64_MAX);
> + if (!object_property_set_link(OBJECT(&a->ssp), "memory",
> + OBJECT(&a->ssp.memory), &error_abort)) {
please use errp instead.
> + return false;
> + }
> +
> + if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
same here.
Thanks,
C.
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> {
> int i;
> + MachineState *ms = MACHINE(qdev_get_machine());
> + MachineClass *mc = MACHINE_GET_CLASS(ms);
> Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
> AspeedSoCState *s = ASPEED_SOC(dev);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> @@ -719,6 +754,13 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
> sc->memmap[ASPEED_DEV_SCUIO]);
>
> + /* Coprocessors */
> + if (mc->default_cpus > sc->num_cpus) {
> + if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
> + return;
> + }
> + }
> +
> /* UART */
> if (!aspeed_soc_uart_realize(s, errp)) {
> return;
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve
2025-09-02 6:20 ` [SPAM] " Cédric Le Goater
@ 2025-09-02 7:27 ` Markus Armbruster
2025-09-02 8:49 ` Jamin Lin
2025-09-02 8:41 ` Jamin Lin
1 sibling, 1 reply; 61+ messages in thread
From: Markus Armbruster @ 2025-09-02 7:27 UTC (permalink / raw)
To: Cédric Le Goater
Cc: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, troy_lee
Cédric Le Goater <clg@kaod.org> writes:
> On 7/17/25 05:40, Jamin Lin wrote:
>> In the previous design, the SSP coprocessor (aspeed27x0ssp-soc) was initialized
>> and realized at the machine level (e.g., AST2700FC). However, to make sure the
>> coprocessors can work together properly—such as using the same SRAM, sharing
>> the SCU, and having consistent memory remapping—we need to change how these
>> devices are set up.
>>
>> This commit moves the SSP coprocessor initialization and realization into the
>> AST2700 SoC (aspeed_soc_ast2700_init() and aspeed_soc_ast2700_realize()).
>> By doing so, the SSP becomes a proper child of the SoC device, rather than
>> the machine.
>>
>> This is a preparation step for future commits that will support shared SCU,
>> SRAM, and memory remap logic—specifically enabling PSP DRAM remap for SSP SDRAM
>> access.
>>
>> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
[...]
>> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
>> index 6aa3841b69..ffbc32fef2 100644
>> --- a/hw/arm/aspeed_ast27x0.c
>> +++ b/hw/arm/aspeed_ast27x0.c
[...]
>> @@ -610,9 +619,35 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
>> return true;
>> }
>> +static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
>
> I would pass 'Aspeed27x0SoCState *' instead.
>
>> +{
>> + Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
>> + AspeedSoCState *s = ASPEED_SOC(dev);
>> + Clock *sysclk;
>> +
>> + sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
>> + clock_set_hz(sysclk, 200000000ULL);
>> + qdev_connect_clock_in(DEVICE(&a->ssp), "sysclk", sysclk);
>> +
>> + memory_region_init(&a->ssp.memory, OBJECT(&a->ssp), "ssp-memory",
>> + UINT64_MAX);
>> + if (!object_property_set_link(OBJECT(&a->ssp), "memory",
>> + OBJECT(&a->ssp.memory), &error_abort)) {
>
> please use errp instead.
>
>> + return false;
>> + }
object_property_set_link() can return false only when it fails, and it
sets an error when it fails. Since you pass &error_abort, it cannot
fail (it aborts instead). Therefore the return value is always true,
and the return statement is dead code.
If object_property_set_link() is not expected to fail, i.e. failure
would be a programming error, use
object_property_set_link(..., &error_abort);
If failure is not a programming error, passing &error_abort is wrong,
and you need to pass errp instead.
>> +
>> + if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
>
> same here.
Same argument.
[...]
^ permalink raw reply [flat|nested] 61+ messages in thread* RE: [SPAM] [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve
2025-09-02 7:27 ` Markus Armbruster
@ 2025-09-02 8:49 ` Jamin Lin
2025-09-02 9:39 ` Markus Armbruster
0 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin @ 2025-09-02 8:49 UTC (permalink / raw)
To: Markus Armbruster, Cédric Le Goater
Cc: Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery, Joel Stanley,
open list:ASPEED BMCs, open list:All patches CC here, Troy Lee
Hi Markus,
> Subject: Re: [SPAM] [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor
> initialization from machine to SoC leve
>
> Cédric Le Goater <clg@kaod.org> writes:
>
> > On 7/17/25 05:40, Jamin Lin wrote:
> >> In the previous design, the SSP coprocessor (aspeed27x0ssp-soc) was
> >> initialized and realized at the machine level (e.g., AST2700FC).
> >> However, to make sure the coprocessors can work together
> >> properly—such as using the same SRAM, sharing the SCU, and having
> >> consistent memory remapping—we need to change how these devices are
> set up.
> >>
> >> This commit moves the SSP coprocessor initialization and realization
> >> into the
> >> AST2700 SoC (aspeed_soc_ast2700_init() and
> aspeed_soc_ast2700_realize()).
> >> By doing so, the SSP becomes a proper child of the SoC device, rather
> >> than the machine.
> >>
> >> This is a preparation step for future commits that will support
> >> shared SCU, SRAM, and memory remap logic—specifically enabling PSP
> >> DRAM remap for SSP SDRAM access.
> >>
> >> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
>
> [...]
>
> >> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
> >> 6aa3841b69..ffbc32fef2 100644
> >> --- a/hw/arm/aspeed_ast27x0.c
> >> +++ b/hw/arm/aspeed_ast27x0.c
>
> [...]
>
> >> @@ -610,9 +619,35 @@ static bool
> aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
> >> return true;
> >> }
> >> +static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error
> >> **errp)
> >
> > I would pass 'Aspeed27x0SoCState *' instead.
> >
> >> +{
> >> + Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
> >> + AspeedSoCState *s = ASPEED_SOC(dev);
> >> + Clock *sysclk;
> >> +
> >> + sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
> >> + clock_set_hz(sysclk, 200000000ULL);
> >> + qdev_connect_clock_in(DEVICE(&a->ssp), "sysclk", sysclk);
> >> +
> >> + memory_region_init(&a->ssp.memory, OBJECT(&a->ssp),
> "ssp-memory",
> >> + UINT64_MAX);
> >> + if (!object_property_set_link(OBJECT(&a->ssp), "memory",
> >> + OBJECT(&a->ssp.memory),
> >> + &error_abort)) {
> >
> > please use errp instead.
> >
> >> + return false;
> >> + }
>
> object_property_set_link() can return false only when it fails, and it sets an
> error when it fails. Since you pass &error_abort, it cannot fail (it aborts
> instead). Therefore the return value is always true, and the return statement
> is dead code.
>
> If object_property_set_link() is not expected to fail, i.e. failure would be a
> programming error, use
>
> object_property_set_link(..., &error_abort);
>
> If failure is not a programming error, passing &error_abort is wrong, and you
> need to pass errp instead.
>
> >> +
> >> + if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
> >
> > same here.
>
Thanks for the detailed explanation - that clarifies the intent and the
difference between using "error_abort" and "errp".
Appreciate your help.
Thanks again Jamin
> Same argument.
>
> [...]
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve
2025-09-02 8:49 ` Jamin Lin
@ 2025-09-02 9:39 ` Markus Armbruster
0 siblings, 0 replies; 61+ messages in thread
From: Markus Armbruster @ 2025-09-02 9:39 UTC (permalink / raw)
To: Jamin Lin
Cc: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here, Troy Lee
To: Jamin Lin <jamin_lin@aspeedtech.com>
Subject: Re: [SPAM] [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve
Gcc: nnml:mail.redhat.xlst.qemu-devel
From: Markus Armbruster <armbru@redhat.com>
--text follows this line--
Jamin Lin <jamin_lin@aspeedtech.com> writes:
> Hi Markus,
[...]
>> object_property_set_link() can return false only when it fails, and it sets an
>> error when it fails. Since you pass &error_abort, it cannot fail (it aborts
>> instead). Therefore the return value is always true, and the return statement
>> is dead code.
>>
>> If object_property_set_link() is not expected to fail, i.e. failure would be a
>> programming error, use
>>
>> object_property_set_link(..., &error_abort);
>>
>> If failure is not a programming error, passing &error_abort is wrong, and you
>> need to pass errp instead.
>>
>> >> +
>> >> + if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
>> >
>> > same here.
>>
>
> Thanks for the detailed explanation - that clarifies the intent and the
> difference between using "error_abort" and "errp".
> Appreciate your help.
> Thanks again Jamin
You're welcome!
^ permalink raw reply [flat|nested] 61+ messages in thread
* RE: [SPAM] [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve
2025-09-02 6:20 ` [SPAM] " Cédric Le Goater
2025-09-02 7:27 ` Markus Armbruster
@ 2025-09-02 8:41 ` Jamin Lin
2025-09-02 13:24 ` Cédric Le Goater
1 sibling, 1 reply; 61+ messages in thread
From: Jamin Lin @ 2025-09-02 8:41 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric
> Subject: Re: [SPAM] [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor
> initialization from machine to SoC leve
>
> On 7/17/25 05:40, Jamin Lin wrote:
> > In the previous design, the SSP coprocessor (aspeed27x0ssp-soc) was
> > initialized and realized at the machine level (e.g., AST2700FC).
> > However, to make sure the coprocessors can work together properly—such
> > as using the same SRAM, sharing the SCU, and having consistent memory
> > remapping—we need to change how these devices are set up.
> >
> > This commit moves the SSP coprocessor initialization and realization
> > into the
> > AST2700 SoC (aspeed_soc_ast2700_init() and
> aspeed_soc_ast2700_realize()).
> > By doing so, the SSP becomes a proper child of the SoC device, rather
> > than the machine.
> >
> > This is a preparation step for future commits that will support shared
> > SCU, SRAM, and memory remap logic—specifically enabling PSP DRAM
> remap
> > for SSP SDRAM access.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > include/hw/arm/aspeed_soc.h | 27 +++++++++++++-----------
> > hw/arm/aspeed_ast27x0-fc.c | 30 ++------------------------
> > hw/arm/aspeed_ast27x0.c | 42
> +++++++++++++++++++++++++++++++++++++
> > 3 files changed, 59 insertions(+), 40 deletions(-)
> >
> > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> > index 217ef0eafd..2831da91ab 100644
> > --- a/include/hw/arm/aspeed_soc.h
> > +++ b/include/hw/arm/aspeed_soc.h
> > @@ -128,6 +128,19 @@ struct Aspeed2600SoCState {
> > #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
> > OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState,
> ASPEED2600_SOC)
> >
> > +struct Aspeed27x0SSPSoCState {
> > + AspeedSoCState parent;
> > + AspeedINTCState intc[2];
> > + UnimplementedDeviceState ipc[2];
> > + UnimplementedDeviceState scuio;
> > + MemoryRegion memory;
> > +
> > + ARMv7MState armv7m;
> > +};
> > +
> > +#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
> > +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState,
> ASPEED27X0SSP_SOC)
> > +
> > struct Aspeed27x0SoCState {
> > AspeedSoCState parent;
> >
> > @@ -135,6 +148,8 @@ struct Aspeed27x0SoCState {
> > AspeedINTCState intc[2];
> > GICv3State gic;
> > MemoryRegion dram_empty;
> > +
> > + Aspeed27x0SSPSoCState ssp;
> > };
> >
> > #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
> > @@ -146,18 +161,6 @@ struct Aspeed10x0SoCState {
> > ARMv7MState armv7m;
> > };
> >
> > -struct Aspeed27x0SSPSoCState {
> > - AspeedSoCState parent;
> > - AspeedINTCState intc[2];
> > - UnimplementedDeviceState ipc[2];
> > - UnimplementedDeviceState scuio;
> > -
> > - ARMv7MState armv7m;
> > -};
> > -
> > -#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
> > -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState,
> ASPEED27X0SSP_SOC)
> > -
> > struct Aspeed27x0TSPSoCState {
> > AspeedSoCState parent;
> > AspeedINTCState intc[2];
> > diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
> > index e2eee6183f..c9b338fe78 100644
> > --- a/hw/arm/aspeed_ast27x0-fc.c
> > +++ b/hw/arm/aspeed_ast27x0-fc.c
> > @@ -37,14 +37,11 @@ struct Ast2700FCState {
> > MemoryRegion ca35_memory;
> > MemoryRegion ca35_dram;
> > MemoryRegion ca35_boot_rom;
> > - MemoryRegion ssp_memory;
> > MemoryRegion tsp_memory;
> >
> > - Clock *ssp_sysclk;
> > Clock *tsp_sysclk;
> >
> > Aspeed27x0SoCState ca35;
> > - Aspeed27x0SSPSoCState ssp;
> > Aspeed27x0TSPSoCState tsp;
> >
> > bool mmio_exec;
> > @@ -158,6 +155,8 @@ static void ast2700fc_ca35_init(MachineState
> *machine)
> > return;
> > }
> > aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0));
> > + aspeed_soc_uart_set_chr(ASPEED_SOC(&s->ca35.ssp),
> ASPEED_DEV_UART4,
> > + serial_hd(1));
>
> hmm, I wonder if the second uart shouldn't be set from the init handler of the
> Aspeed27x0SSPSoCState child object.
Will try it.
>
>
> > if (!qdev_realize(DEVICE(&s->ca35), NULL, &error_abort)) {
> > return;
> > }
> > @@ -196,30 +195,6 @@ static void ast2700fc_ca35_init(MachineState
> *machine)
> > arm_load_kernel(ARM_CPU(first_cpu), machine,
> &ast2700fc_board_info);
> > }
> >
> > -static void ast2700fc_ssp_init(MachineState *machine) -{
> > - AspeedSoCState *soc;
> > - Ast2700FCState *s = AST2700A1FC(machine);
> > - s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
> > - clock_set_hz(s->ssp_sysclk, 200000000ULL);
> > -
> > - object_initialize_child(OBJECT(s), "ssp", &s->ssp,
> TYPE_ASPEED27X0SSP_SOC);
> > - memory_region_init(&s->ssp_memory, OBJECT(&s->ssp),
> "ssp-memory",
> > - UINT64_MAX);
> > -
> > - qdev_connect_clock_in(DEVICE(&s->ssp), "sysclk", s->ssp_sysclk);
> > - if (!object_property_set_link(OBJECT(&s->ssp), "memory",
> > - OBJECT(&s->ssp_memory),
> &error_abort)) {
> > - return;
> > - }
> > -
> > - soc = ASPEED_SOC(&s->ssp);
> > - aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART4, serial_hd(1));
> > - if (!qdev_realize(DEVICE(&s->ssp), NULL, &error_abort)) {
> > - return;
> > - }
> > -}
> > -
> > static void ast2700fc_tsp_init(MachineState *machine)
> > {
> > AspeedSoCState *soc;
> > @@ -247,7 +222,6 @@ static void ast2700fc_tsp_init(MachineState
> *machine)
> > static void ast2700fc_init(MachineState *machine)
> > {
> > ast2700fc_ca35_init(machine);
> > - ast2700fc_ssp_init(machine);
> > ast2700fc_tsp_init(machine);
> > }
> >
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
> > 6aa3841b69..ffbc32fef2 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -22,6 +22,8 @@
> > #include "hw/intc/arm_gicv3.h"
> > #include "qobject/qlist.h"
> > #include "qemu/log.h"
> > +#include "hw/qdev-clock.h"
> > +#include "hw/boards.h"
> >
> > #define AST2700_SOC_IO_SIZE 0x00FE0000
> > #define AST2700_SOC_IOMEM_SIZE 0x01000000
> > @@ -410,6 +412,8 @@ static bool
> > aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp)
> >
> > static void aspeed_soc_ast2700_init(Object *obj)
> > {
> > + MachineState *ms = MACHINE(qdev_get_machine());
>
> Calling qdev_get_machine() in a device model is a no-no. Please don't.
Will remove it.
>
> > + MachineClass *mc = MACHINE_GET_CLASS(ms);
> > Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj);
> > AspeedSoCState *s = ASPEED_SOC(obj);
> > AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); @@ -426,6
> +430,11
> > @@ static void aspeed_soc_ast2700_init(Object *obj)
> > aspeed_soc_cpu_type(sc));
> > }
> >
> > + /* Coprocessors */
> > + if (mc->default_cpus > sc->num_cpus) {
>
> That's a hack.
>
> We need to find another way to conditionally create the co-processors if that's
> what you want to do. A SoC class attribute would be a better way.
>
If I understanding your suggestion correctly, I should create new SOC variant(ex: ast2700-fc) and set a class attribute in its class_init.
Then, the SOC's init/realize will check the coprocessor features and initialize SSP/TSP objects accordingly.
If yes, I will add a new class attribute(ex: sc->coprocessor =2)
> > + object_initialize_child(obj, "ssp", &a->ssp,
> TYPE_ASPEED27X0SSP_SOC);
> > + }
> > +
> > object_initialize_child(obj, "gic", &a->gic,
> > gicv3_class_name());
> >
> > object_initialize_child(obj, "scu", &s->scu,
> > TYPE_ASPEED_2700_SCU); @@ -610,9 +619,35 @@ static bool
> aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
> > return true;
> > }
> >
> > +static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error
> > +**errp)
>
> I would pass 'Aspeed27x0SoCState *' instead.
>
Will do
> > +{
> > + Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
> > + AspeedSoCState *s = ASPEED_SOC(dev);
> > + Clock *sysclk;
> > +
> > + sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
> > + clock_set_hz(sysclk, 200000000ULL);
> > + qdev_connect_clock_in(DEVICE(&a->ssp), "sysclk", sysclk);
> > +
> > + memory_region_init(&a->ssp.memory, OBJECT(&a->ssp),
> "ssp-memory",
> > + UINT64_MAX);
> > + if (!object_property_set_link(OBJECT(&a->ssp), "memory",
> > + OBJECT(&a->ssp.memory),
> > + &error_abort)) {
>
> please use errp instead.
>
Will do
>
> > + return false;
> > + }
> > +
> > + if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
>
> same here.
>
Will do
Thanks for review and suggestions.
Jamin
>
> Thanks,
>
> C.
>
>
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> > {
> > int i;
> > + MachineState *ms = MACHINE(qdev_get_machine());
> > + MachineClass *mc = MACHINE_GET_CLASS(ms);
> > Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
> > AspeedSoCState *s = ASPEED_SOC(dev);
> > AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); @@ -719,6
> +754,13
> > @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> > aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
> > sc->memmap[ASPEED_DEV_SCUIO]);
> >
> > + /* Coprocessors */
> > + if (mc->default_cpus > sc->num_cpus) {
> > + if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
> > + return;
> > + }
> > + }
> > +
> > /* UART */
> > if (!aspeed_soc_uart_realize(s, errp)) {
> > return;
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve
2025-09-02 8:41 ` Jamin Lin
@ 2025-09-02 13:24 ` Cédric Le Goater
0 siblings, 0 replies; 61+ messages in thread
From: Cédric Le Goater @ 2025-09-02 13:24 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
On 9/2/25 10:41, Jamin Lin wrote:
> Hi Cédric
>
>> Subject: Re: [SPAM] [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor
>> initialization from machine to SoC leve
>>
>> On 7/17/25 05:40, Jamin Lin wrote:
>>> In the previous design, the SSP coprocessor (aspeed27x0ssp-soc) was
>>> initialized and realized at the machine level (e.g., AST2700FC).
>>> However, to make sure the coprocessors can work together properly—such
>>> as using the same SRAM, sharing the SCU, and having consistent memory
>>> remapping—we need to change how these devices are set up.
>>>
>>> This commit moves the SSP coprocessor initialization and realization
>>> into the
>>> AST2700 SoC (aspeed_soc_ast2700_init() and
>> aspeed_soc_ast2700_realize()).
>>> By doing so, the SSP becomes a proper child of the SoC device, rather
>>> than the machine.
>>>
>>> This is a preparation step for future commits that will support shared
>>> SCU, SRAM, and memory remap logic—specifically enabling PSP DRAM
>> remap
>>> for SSP SDRAM access.
>>>
>>> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
>>> ---
>>> include/hw/arm/aspeed_soc.h | 27 +++++++++++++-----------
>>> hw/arm/aspeed_ast27x0-fc.c | 30 ++------------------------
>>> hw/arm/aspeed_ast27x0.c | 42
>> +++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 59 insertions(+), 40 deletions(-)
>>>
>>> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
>>> index 217ef0eafd..2831da91ab 100644
>>> --- a/include/hw/arm/aspeed_soc.h
>>> +++ b/include/hw/arm/aspeed_soc.h
>>> @@ -128,6 +128,19 @@ struct Aspeed2600SoCState {
>>> #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
>>> OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState,
>> ASPEED2600_SOC)
>>>
>>> +struct Aspeed27x0SSPSoCState {
>>> + AspeedSoCState parent;
>>> + AspeedINTCState intc[2];
>>> + UnimplementedDeviceState ipc[2];
>>> + UnimplementedDeviceState scuio;
>>> + MemoryRegion memory;
>>> +
>>> + ARMv7MState armv7m;
>>> +};
>>> +
>>> +#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
>>> +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState,
>> ASPEED27X0SSP_SOC)
>>> +
>>> struct Aspeed27x0SoCState {
>>> AspeedSoCState parent;
>>>
>>> @@ -135,6 +148,8 @@ struct Aspeed27x0SoCState {
>>> AspeedINTCState intc[2];
>>> GICv3State gic;
>>> MemoryRegion dram_empty;
>>> +
>>> + Aspeed27x0SSPSoCState ssp;
>>> };
>>>
>>> #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
>>> @@ -146,18 +161,6 @@ struct Aspeed10x0SoCState {
>>> ARMv7MState armv7m;
>>> };
>>>
>>> -struct Aspeed27x0SSPSoCState {
>>> - AspeedSoCState parent;
>>> - AspeedINTCState intc[2];
>>> - UnimplementedDeviceState ipc[2];
>>> - UnimplementedDeviceState scuio;
>>> -
>>> - ARMv7MState armv7m;
>>> -};
>>> -
>>> -#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
>>> -OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState,
>> ASPEED27X0SSP_SOC)
>>> -
>>> struct Aspeed27x0TSPSoCState {
>>> AspeedSoCState parent;
>>> AspeedINTCState intc[2];
>>> diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
>>> index e2eee6183f..c9b338fe78 100644
>>> --- a/hw/arm/aspeed_ast27x0-fc.c
>>> +++ b/hw/arm/aspeed_ast27x0-fc.c
>>> @@ -37,14 +37,11 @@ struct Ast2700FCState {
>>> MemoryRegion ca35_memory;
>>> MemoryRegion ca35_dram;
>>> MemoryRegion ca35_boot_rom;
>>> - MemoryRegion ssp_memory;
>>> MemoryRegion tsp_memory;
>>>
>>> - Clock *ssp_sysclk;
>>> Clock *tsp_sysclk;
>>>
>>> Aspeed27x0SoCState ca35;
>>> - Aspeed27x0SSPSoCState ssp;
>>> Aspeed27x0TSPSoCState tsp;
>>>
>>> bool mmio_exec;
>>> @@ -158,6 +155,8 @@ static void ast2700fc_ca35_init(MachineState
>> *machine)
>>> return;
>>> }
>>> aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0));
>>> + aspeed_soc_uart_set_chr(ASPEED_SOC(&s->ca35.ssp),
>> ASPEED_DEV_UART4,
>>> + serial_hd(1));
>>
>> hmm, I wonder if the second uart shouldn't be set from the init handler of the
>> Aspeed27x0SSPSoCState child object.
>
> Will try it.
>
>>
>>
>>> if (!qdev_realize(DEVICE(&s->ca35), NULL, &error_abort)) {
>>> return;
>>> }
>>> @@ -196,30 +195,6 @@ static void ast2700fc_ca35_init(MachineState
>> *machine)
>>> arm_load_kernel(ARM_CPU(first_cpu), machine,
>> &ast2700fc_board_info);
>>> }
>>>
>>> -static void ast2700fc_ssp_init(MachineState *machine) -{
>>> - AspeedSoCState *soc;
>>> - Ast2700FCState *s = AST2700A1FC(machine);
>>> - s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
>>> - clock_set_hz(s->ssp_sysclk, 200000000ULL);
>>> -
>>> - object_initialize_child(OBJECT(s), "ssp", &s->ssp,
>> TYPE_ASPEED27X0SSP_SOC);
>>> - memory_region_init(&s->ssp_memory, OBJECT(&s->ssp),
>> "ssp-memory",
>>> - UINT64_MAX);
>>> -
>>> - qdev_connect_clock_in(DEVICE(&s->ssp), "sysclk", s->ssp_sysclk);
>>> - if (!object_property_set_link(OBJECT(&s->ssp), "memory",
>>> - OBJECT(&s->ssp_memory),
>> &error_abort)) {
>>> - return;
>>> - }
>>> -
>>> - soc = ASPEED_SOC(&s->ssp);
>>> - aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART4, serial_hd(1));
>>> - if (!qdev_realize(DEVICE(&s->ssp), NULL, &error_abort)) {
>>> - return;
>>> - }
>>> -}
>>> -
>>> static void ast2700fc_tsp_init(MachineState *machine)
>>> {
>>> AspeedSoCState *soc;
>>> @@ -247,7 +222,6 @@ static void ast2700fc_tsp_init(MachineState
>> *machine)
>>> static void ast2700fc_init(MachineState *machine)
>>> {
>>> ast2700fc_ca35_init(machine);
>>> - ast2700fc_ssp_init(machine);
>>> ast2700fc_tsp_init(machine);
>>> }
>>>
>>> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
>>> 6aa3841b69..ffbc32fef2 100644
>>> --- a/hw/arm/aspeed_ast27x0.c
>>> +++ b/hw/arm/aspeed_ast27x0.c
>>> @@ -22,6 +22,8 @@
>>> #include "hw/intc/arm_gicv3.h"
>>> #include "qobject/qlist.h"
>>> #include "qemu/log.h"
>>> +#include "hw/qdev-clock.h"
>>> +#include "hw/boards.h"
>>>
>>> #define AST2700_SOC_IO_SIZE 0x00FE0000
>>> #define AST2700_SOC_IOMEM_SIZE 0x01000000
>>> @@ -410,6 +412,8 @@ static bool
>>> aspeed_soc_ast2700_dram_init(DeviceState *dev, Error **errp)
>>>
>>> static void aspeed_soc_ast2700_init(Object *obj)
>>> {
>>> + MachineState *ms = MACHINE(qdev_get_machine());
>>
>> Calling qdev_get_machine() in a device model is a no-no. Please don't.
>
> Will remove it.
>
>>
>>> + MachineClass *mc = MACHINE_GET_CLASS(ms);
>>> Aspeed27x0SoCState *a = ASPEED27X0_SOC(obj);
>>> AspeedSoCState *s = ASPEED_SOC(obj);
>>> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); @@ -426,6
>> +430,11
>>> @@ static void aspeed_soc_ast2700_init(Object *obj)
>>> aspeed_soc_cpu_type(sc));
>>> }
>>>
>>> + /* Coprocessors */
>>> + if (mc->default_cpus > sc->num_cpus) {
>>
>> That's a hack.
>>
>> We need to find another way to conditionally create the co-processors if that's
>> what you want to do. A SoC class attribute would be a better way.
>>
>
> If I understanding your suggestion correctly, I should create new SOC variant(ex: ast2700-fc) and set a class attribute in its class_init.
Yes. Something like that.
Thanks,
C.
> Then, the SOC's init/realize will check the coprocessor features and initialize SSP/TSP objects accordingly.
> If yes, I will add a new class attribute(ex: sc->coprocessor =2)
>
>>> + object_initialize_child(obj, "ssp", &a->ssp,
>> TYPE_ASPEED27X0SSP_SOC);
>>> + }
>>> +
>>> object_initialize_child(obj, "gic", &a->gic,
>>> gicv3_class_name());
>>>
>>> object_initialize_child(obj, "scu", &s->scu,
>>> TYPE_ASPEED_2700_SCU); @@ -610,9 +619,35 @@ static bool
>> aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
>>> return true;
>>> }
>>>
>>> +static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error
>>> +**errp)
>>
>> I would pass 'Aspeed27x0SoCState *' instead.
>>
>
>
> Will do
>
>>> +{
>>> + Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
>>> + AspeedSoCState *s = ASPEED_SOC(dev);
>>> + Clock *sysclk;
>>> +
>>> + sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
>>> + clock_set_hz(sysclk, 200000000ULL);
>>> + qdev_connect_clock_in(DEVICE(&a->ssp), "sysclk", sysclk);
>>> +
>>> + memory_region_init(&a->ssp.memory, OBJECT(&a->ssp),
>> "ssp-memory",
>>> + UINT64_MAX);
>>> + if (!object_property_set_link(OBJECT(&a->ssp), "memory",
>>> + OBJECT(&a->ssp.memory),
>>> + &error_abort)) {
>>
>> please use errp instead.
>>
> Will do
>>
>>> + return false;
>>> + }
>>> +
>>> + if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
>>
>> same here.
>>
> Will do
>
> Thanks for review and suggestions.
> Jamin
>>
>> Thanks,
>>
>> C.
>>
>>
>>> + return false;
>>> + }
>>> +
>>> + return true;
>>> +}
>>> +
>>> static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
>>> {
>>> int i;
>>> + MachineState *ms = MACHINE(qdev_get_machine());
>>> + MachineClass *mc = MACHINE_GET_CLASS(ms);
>>> Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
>>> AspeedSoCState *s = ASPEED_SOC(dev);
>>> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); @@ -719,6
>> +754,13
>>> @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
>>> aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
>>> sc->memmap[ASPEED_DEV_SCUIO]);
>>>
>>> + /* Coprocessors */
>>> + if (mc->default_cpus > sc->num_cpus) {
>>> + if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
>>> + return;
>>> + }
>>> + }
>>> +
>>> /* UART */
>>> if (!aspeed_soc_uart_realize(s, errp)) {
>>> return;
>
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v1 03/21] hw/arm/ast27x0: Move TSP coprocessor initialization from machine to SoC leve
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support VBootRom Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 04/21] hw/arm/aspeed_ast27x0-ssp: Switch SSP memory to SDRAM and use dram_container for remap support Jamin Lin via
` (18 subsequent siblings)
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
In the previous design, the TSP coprocessor (aspeed27x0tsp-soc) was initialized
and realized at the machine level (e.g., AST2700FC). To allow proper
integration between coprocessors—such as shared use of SRAM, SCU, and memory
remap configuration—this commit moves TSP initialization into the AST2700 SoC.
By handling TSP initialization and realization at the SoC level, it becomes
easier to manage device ordering and ensure correct dependencies between
coprocessors and controllers. It also reflects the hardware design more
accurately, as these processors belong to the SoC, not the board.
Benefits of this change:
- TSP can share SCU, SRAM, and memory regions with other SoC devices.
- Centralizes coprocessor setup logic under SoC for better maintenance.
- Simplifies machine-level code in "aspeed_ast27x0-fc.c".
This is part of ongoing work to support shared SCU, SRAM, and memory remap
handling across PSP, SSP, and TSP. Future commits will add memory remap
mechanisms and tightly integrated SoC controller coordination.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 26 ++++++++++++++------------
hw/arm/aspeed_ast27x0-fc.c | 32 ++------------------------------
hw/arm/aspeed_ast27x0.c | 28 ++++++++++++++++++++++++++++
3 files changed, 44 insertions(+), 42 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 2831da91ab..3dd317cfee 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -141,6 +141,19 @@ struct Aspeed27x0SSPSoCState {
#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
+struct Aspeed27x0TSPSoCState {
+ AspeedSoCState parent;
+ AspeedINTCState intc[2];
+ UnimplementedDeviceState ipc[2];
+ UnimplementedDeviceState scuio;
+ MemoryRegion memory;
+
+ ARMv7MState armv7m;
+};
+
+#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC)
+
struct Aspeed27x0SoCState {
AspeedSoCState parent;
@@ -150,6 +163,7 @@ struct Aspeed27x0SoCState {
MemoryRegion dram_empty;
Aspeed27x0SSPSoCState ssp;
+ Aspeed27x0TSPSoCState tsp;
};
#define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
@@ -161,18 +175,6 @@ struct Aspeed10x0SoCState {
ARMv7MState armv7m;
};
-struct Aspeed27x0TSPSoCState {
- AspeedSoCState parent;
- AspeedINTCState intc[2];
- UnimplementedDeviceState ipc[2];
- UnimplementedDeviceState scuio;
-
- ARMv7MState armv7m;
-};
-
-#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc"
-OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC)
-
#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index c9b338fe78..eb25a2635b 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -37,18 +37,13 @@ struct Ast2700FCState {
MemoryRegion ca35_memory;
MemoryRegion ca35_dram;
MemoryRegion ca35_boot_rom;
- MemoryRegion tsp_memory;
-
- Clock *tsp_sysclk;
Aspeed27x0SoCState ca35;
- Aspeed27x0TSPSoCState tsp;
bool mmio_exec;
};
#define AST2700FC_BMC_RAM_SIZE (1 * GiB)
-#define AST2700FC_CM4_DRAM_SIZE (32 * MiB)
#define AST2700FC_HW_STRAP1 0x000000C0
#define AST2700FC_HW_STRAP2 0x00000003
@@ -157,6 +152,8 @@ static void ast2700fc_ca35_init(MachineState *machine)
aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0));
aspeed_soc_uart_set_chr(ASPEED_SOC(&s->ca35.ssp), ASPEED_DEV_UART4,
serial_hd(1));
+ aspeed_soc_uart_set_chr(ASPEED_SOC(&s->ca35.tsp), ASPEED_DEV_UART7,
+ serial_hd(2));
if (!qdev_realize(DEVICE(&s->ca35), NULL, &error_abort)) {
return;
}
@@ -195,34 +192,9 @@ static void ast2700fc_ca35_init(MachineState *machine)
arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
}
-static void ast2700fc_tsp_init(MachineState *machine)
-{
- AspeedSoCState *soc;
- Ast2700FCState *s = AST2700A1FC(machine);
- s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
- clock_set_hz(s->tsp_sysclk, 200000000ULL);
-
- object_initialize_child(OBJECT(s), "tsp", &s->tsp, TYPE_ASPEED27X0TSP_SOC);
- memory_region_init(&s->tsp_memory, OBJECT(&s->tsp), "tsp-memory",
- UINT64_MAX);
-
- qdev_connect_clock_in(DEVICE(&s->tsp), "sysclk", s->tsp_sysclk);
- if (!object_property_set_link(OBJECT(&s->tsp), "memory",
- OBJECT(&s->tsp_memory), &error_abort)) {
- return;
- }
-
- soc = ASPEED_SOC(&s->tsp);
- aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART7, serial_hd(2));
- if (!qdev_realize(DEVICE(&s->tsp), NULL, &error_abort)) {
- return;
- }
-}
-
static void ast2700fc_init(MachineState *machine)
{
ast2700fc_ca35_init(machine);
- ast2700fc_tsp_init(machine);
}
static void ast2700fc_class_init(ObjectClass *oc, const void *data)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index ffbc32fef2..665627f788 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -433,6 +433,7 @@ static void aspeed_soc_ast2700_init(Object *obj)
/* Coprocessors */
if (mc->default_cpus > sc->num_cpus) {
object_initialize_child(obj, "ssp", &a->ssp, TYPE_ASPEED27X0SSP_SOC);
+ object_initialize_child(obj, "tsp", &a->tsp, TYPE_ASPEED27X0TSP_SOC);
}
object_initialize_child(obj, "gic", &a->gic, gicv3_class_name());
@@ -643,6 +644,30 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
return true;
}
+static bool aspeed_soc_ast2700_tsp_realize(DeviceState *dev, Error **errp)
+{
+ Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
+ AspeedSoCState *s = ASPEED_SOC(dev);
+ Clock *sysclk;
+
+ sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
+ clock_set_hz(sysclk, 200000000ULL);
+ qdev_connect_clock_in(DEVICE(&a->tsp), "sysclk", sysclk);
+
+ memory_region_init(&a->tsp.memory, OBJECT(&a->tsp), "tsp-memory",
+ UINT64_MAX);
+ if (!object_property_set_link(OBJECT(&a->tsp), "memory",
+ OBJECT(&a->tsp.memory), &error_abort)) {
+ return false;
+ }
+
+ if (!qdev_realize(DEVICE(&a->tsp), NULL, &error_abort)) {
+ return false;
+ }
+
+ return true;
+}
+
static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
{
int i;
@@ -759,6 +784,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
return;
}
+ if (!aspeed_soc_ast2700_tsp_realize(dev, errp)) {
+ return;
+ }
}
/* UART */
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 04/21] hw/arm/aspeed_ast27x0-ssp: Switch SSP memory to SDRAM and use dram_container for remap support
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (2 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 03/21] hw/arm/ast27x0: Move TSP " Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-09-02 7:36 ` [SPAM] " Cédric Le Goater
2025-07-17 3:40 ` [PATCH v1 05/21] hw/arm/aspeed_ast27x0-tsp: Switch TSP " Jamin Lin via
` (17 subsequent siblings)
21 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
According to the AST2700 design, the SSP coprocessor uses its own SDRAM
instead of SRAM. Additionally, all three coprocessors—SSP, TSP, and PSP—share
a common SRAM block. In the previous implementation, the SSP memory region
was labeled and sized as "SRAM", but in practice it was being used as SSP's
local SDRAM.
This commit updates the SSP memory mapping to reflect the correct hardware
design:
- Replace the SRAM region with a "512MB SDRAM" region starting at 0x0.
- Rename the internal variable from "sram" to "dram_container" for clarity.
- Use "AST2700_SSP_SDRAM_SIZE" (512MB) instead of the previous 32MB SRAM size.
- Map the new region using "ASPEED_DEV_SDRAM" instead of "ASPEED_DEV_SRAM".
This change also prepares for future enhancements where PSP DRAM will be
remapped into this SSP SDRAM container using subregions at specific offsets.
Using "dram_container" makes it easier to manage aliases and remap logic.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0-ssp.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 80ec5996c1..9641e27de1 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -15,10 +15,10 @@
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
-#define AST2700_SSP_RAM_SIZE (32 * MiB)
+#define AST2700_SSP_SDRAM_SIZE (512 * MiB)
static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
- [ASPEED_DEV_SRAM] = 0x00000000,
+ [ASPEED_DEV_SDRAM] = 0x00000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
@@ -163,7 +163,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
AspeedSoCState *s = ASPEED_SOC(dev_soc);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
DeviceState *armv7m;
- g_autofree char *sram_name = NULL;
+ g_autofree char *name = NULL;
int i;
if (!clock_has_source(s->sysclk)) {
@@ -180,16 +180,17 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
OBJECT(s->memory), &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
- sram_name = g_strdup_printf("aspeed.dram.%d",
- CPU(a->armv7m.cpu)->cpu_index);
+ /* SDRAM */
+ name = g_strdup_printf("aspeed.sdram-container.%d",
+ CPU(a->armv7m.cpu)->cpu_index);
- if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
- errp)) {
+ if (!memory_region_init_ram(&s->dram_container, OBJECT(s), name,
+ AST2700_SSP_SDRAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM],
- &s->sram);
+ sc->memmap[ASPEED_DEV_SDRAM],
+ &s->dram_container);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
@@ -268,7 +269,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass, const void *dat
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2700_A1_SILICON_REV;
- sc->sram_size = AST2700_SSP_RAM_SIZE;
sc->spis_num = 0;
sc->ehcis_num = 0;
sc->wdts_num = 0;
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 04/21] hw/arm/aspeed_ast27x0-ssp: Switch SSP memory to SDRAM and use dram_container for remap support
2025-07-17 3:40 ` [PATCH v1 04/21] hw/arm/aspeed_ast27x0-ssp: Switch SSP memory to SDRAM and use dram_container for remap support Jamin Lin via
@ 2025-09-02 7:36 ` Cédric Le Goater
2025-09-03 1:45 ` Jamin Lin
0 siblings, 1 reply; 61+ messages in thread
From: Cédric Le Goater @ 2025-09-02 7:36 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 7/17/25 05:40, Jamin Lin wrote:
> According to the AST2700 design, the SSP coprocessor uses its own SDRAM
> instead of SRAM. Additionally, all three coprocessors—SSP, TSP, and PSP—share
> a common SRAM block. In the previous implementation, the SSP memory region
> was labeled and sized as "SRAM", but in practice it was being used as SSP's
> local SDRAM.
So the SSP coprocessor has no SRAM ?
>
> This commit updates the SSP memory mapping to reflect the correct hardware
> design:
>
> - Replace the SRAM region with a "512MB SDRAM" region starting at 0x0.
Is 512MB a real HW value ?
Thanks,
C.
> - Rename the internal variable from "sram" to "dram_container" for clarity.
> - Use "AST2700_SSP_SDRAM_SIZE" (512MB) instead of the previous 32MB SRAM size.
> - Map the new region using "ASPEED_DEV_SDRAM" instead of "ASPEED_DEV_SRAM".
>
> This change also prepares for future enhancements where PSP DRAM will be
> remapped into this SSP SDRAM container using subregions at specific offsets.
> Using "dram_container" makes it easier to manage aliases and remap logic.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> hw/arm/aspeed_ast27x0-ssp.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
> index 80ec5996c1..9641e27de1 100644
> --- a/hw/arm/aspeed_ast27x0-ssp.c
> +++ b/hw/arm/aspeed_ast27x0-ssp.c
> @@ -15,10 +15,10 @@
> #include "hw/misc/unimp.h"
> #include "hw/arm/aspeed_soc.h"
>
> -#define AST2700_SSP_RAM_SIZE (32 * MiB)
> +#define AST2700_SSP_SDRAM_SIZE (512 * MiB)
>
> static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
> - [ASPEED_DEV_SRAM] = 0x00000000,
> + [ASPEED_DEV_SDRAM] = 0x00000000,
> [ASPEED_DEV_INTC] = 0x72100000,
> [ASPEED_DEV_SCU] = 0x72C02000,
> [ASPEED_DEV_SCUIO] = 0x74C02000,
> @@ -163,7 +163,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
> AspeedSoCState *s = ASPEED_SOC(dev_soc);
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> DeviceState *armv7m;
> - g_autofree char *sram_name = NULL;
> + g_autofree char *name = NULL;
> int i;
>
> if (!clock_has_source(s->sysclk)) {
> @@ -180,16 +180,17 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
> OBJECT(s->memory), &error_abort);
> sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
>
> - sram_name = g_strdup_printf("aspeed.dram.%d",
> - CPU(a->armv7m.cpu)->cpu_index);
> + /* SDRAM */
> + name = g_strdup_printf("aspeed.sdram-container.%d",
> + CPU(a->armv7m.cpu)->cpu_index);
>
> - if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
> - errp)) {
> + if (!memory_region_init_ram(&s->dram_container, OBJECT(s), name,
> + AST2700_SSP_SDRAM_SIZE, errp)) {
> return;
> }
> memory_region_add_subregion(s->memory,
> - sc->memmap[ASPEED_DEV_SRAM],
> - &s->sram);
> + sc->memmap[ASPEED_DEV_SDRAM],
> + &s->dram_container);
>
> /* SCU */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
> @@ -268,7 +269,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass, const void *dat
>
> sc->valid_cpu_types = valid_cpu_types;
> sc->silicon_rev = AST2700_A1_SILICON_REV;
> - sc->sram_size = AST2700_SSP_RAM_SIZE;
> sc->spis_num = 0;
> sc->ehcis_num = 0;
> sc->wdts_num = 0;
^ permalink raw reply [flat|nested] 61+ messages in thread* RE: [SPAM] [PATCH v1 04/21] hw/arm/aspeed_ast27x0-ssp: Switch SSP memory to SDRAM and use dram_container for remap support
2025-09-02 7:36 ` [SPAM] " Cédric Le Goater
@ 2025-09-03 1:45 ` Jamin Lin
0 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin @ 2025-09-03 1:45 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric
> Subject: Re: [SPAM] [PATCH v1 04/21] hw/arm/aspeed_ast27x0-ssp: Switch SSP
> memory to SDRAM and use dram_container for remap support
>
> On 7/17/25 05:40, Jamin Lin wrote:
> > According to the AST2700 design, the SSP coprocessor uses its own
> > SDRAM instead of SRAM. Additionally, all three coprocessors—SSP, TSP,
> > and PSP—share a common SRAM block. In the previous implementation, the
> > SSP memory region was labeled and sized as "SRAM", but in practice it
> > was being used as SSP's local SDRAM.
>
>
> So the SSP coprocessor has no SRAM ?
Thanks for review.
Yes, both the coprocessor and the PSP(Cortex A35) share the same SRAM.
>
>
> >
> > This commit updates the SSP memory mapping to reflect the correct
> > hardware
> > design:
> >
> > - Replace the SRAM region with a "512MB SDRAM" region starting at 0x0.
>
> Is 512MB a real HW value ?
>
Yes, the SDRAM size is 512MB in a real HW.
Jamin
>
> Thanks,
>
> C.
>
>
>
> > - Rename the internal variable from "sram" to "dram_container" for clarity.
> > - Use "AST2700_SSP_SDRAM_SIZE" (512MB) instead of the previous 32MB
> SRAM size.
> > - Map the new region using "ASPEED_DEV_SDRAM" instead of
> "ASPEED_DEV_SRAM".
> >
> > This change also prepares for future enhancements where PSP DRAM will
> > be remapped into this SSP SDRAM container using subregions at specific
> offsets.
> > Using "dram_container" makes it easier to manage aliases and remap logic.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > hw/arm/aspeed_ast27x0-ssp.c | 20 ++++++++++----------
> > 1 file changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
> > index 80ec5996c1..9641e27de1 100644
> > --- a/hw/arm/aspeed_ast27x0-ssp.c
> > +++ b/hw/arm/aspeed_ast27x0-ssp.c
> > @@ -15,10 +15,10 @@
> > #include "hw/misc/unimp.h"
> > #include "hw/arm/aspeed_soc.h"
> >
> > -#define AST2700_SSP_RAM_SIZE (32 * MiB)
> > +#define AST2700_SSP_SDRAM_SIZE (512 * MiB)
> >
> > static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
> > - [ASPEED_DEV_SRAM] = 0x00000000,
> > + [ASPEED_DEV_SDRAM] = 0x00000000,
> > [ASPEED_DEV_INTC] = 0x72100000,
> > [ASPEED_DEV_SCU] = 0x72C02000,
> > [ASPEED_DEV_SCUIO] = 0x74C02000,
> > @@ -163,7 +163,7 @@ static void
> aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
> > AspeedSoCState *s = ASPEED_SOC(dev_soc);
> > AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> > DeviceState *armv7m;
> > - g_autofree char *sram_name = NULL;
> > + g_autofree char *name = NULL;
> > int i;
> >
> > if (!clock_has_source(s->sysclk)) { @@ -180,16 +180,17 @@ static
> > void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
> > OBJECT(s->memory), &error_abort);
> > sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
> >
> > - sram_name = g_strdup_printf("aspeed.dram.%d",
> > - CPU(a->armv7m.cpu)->cpu_index);
> > + /* SDRAM */
> > + name = g_strdup_printf("aspeed.sdram-container.%d",
> > + CPU(a->armv7m.cpu)->cpu_index);
> >
> > - if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name,
> sc->sram_size,
> > - errp)) {
> > + if (!memory_region_init_ram(&s->dram_container, OBJECT(s), name,
> > + AST2700_SSP_SDRAM_SIZE, errp)) {
> > return;
> > }
> > memory_region_add_subregion(s->memory,
> > - sc->memmap[ASPEED_DEV_SRAM],
> > - &s->sram);
> > +
> sc->memmap[ASPEED_DEV_SDRAM],
> > + &s->dram_container);
> >
> > /* SCU */
> > if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { @@ -268,7
> > +269,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass
> > *klass, const void *dat
> >
> > sc->valid_cpu_types = valid_cpu_types;
> > sc->silicon_rev = AST2700_A1_SILICON_REV;
> > - sc->sram_size = AST2700_SSP_RAM_SIZE;
> > sc->spis_num = 0;
> > sc->ehcis_num = 0;
> > sc->wdts_num = 0;
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v1 05/21] hw/arm/aspeed_ast27x0-tsp: Switch TSP memory to SDRAM and use dram_container for remap support
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (3 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 04/21] hw/arm/aspeed_ast27x0-ssp: Switch SSP memory to SDRAM and use dram_container for remap support Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 06/21] hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device realization order Jamin Lin via
` (16 subsequent siblings)
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
According to the AST2700 design, the TSP coprocessor uses its own SDRAM
instead of SRAM. Additionally, all three coprocessors—SSP, TSP, and PSP—share
a common SRAM block. In the previous implementation, the TSP memory region
was labeled and sized as "SRAM", but in practice it was being used as TSP's
local SDRAM.
This commit updates the TSP memory mapping to reflect the correct hardware
design:
- Replace the SRAM region with a 512MB SDRAM region starting at 0x0.
- Rename the internal variable from `sram` to `dram_container` for clarity.
- Use "AST2700_TSP_SDRAM_SIZE" (512MB) instead of the previous 32MB SRAM size.
- Map the new region using "ASPEED_DEV_SDRAM" instead of "ASPEED_DEV_SRAM".
This change also prepares for future enhancements where PSP DRAM will be
remapped into this TSP SDRAM container using subregions at specific offsets.
Using "dram_container" makes it easier to manage aliases and remap logic.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0-tsp.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 4e0efaef07..a70e30fc16 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -15,10 +15,10 @@
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
-#define AST2700_TSP_RAM_SIZE (32 * MiB)
+#define AST2700_TSP_SDRAM_SIZE (512 * MiB)
static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
- [ASPEED_DEV_SRAM] = 0x00000000,
+ [ASPEED_DEV_SDRAM] = 0x00000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
@@ -163,7 +163,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
AspeedSoCState *s = ASPEED_SOC(dev_soc);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
DeviceState *armv7m;
- g_autofree char *sram_name = NULL;
+ g_autofree char *name = NULL;
int i;
if (!clock_has_source(s->sysclk)) {
@@ -180,16 +180,17 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
OBJECT(s->memory), &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
- sram_name = g_strdup_printf("aspeed.dram.%d",
- CPU(a->armv7m.cpu)->cpu_index);
+ /* SDRAM */
+ name = g_strdup_printf("aspeed.sdram-container.%d",
+ CPU(a->armv7m.cpu)->cpu_index);
- if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
- errp)) {
+ if (!memory_region_init_ram(&s->dram_container, OBJECT(s), name,
+ AST2700_TSP_SDRAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM],
- &s->sram);
+ sc->memmap[ASPEED_DEV_SDRAM],
+ &s->dram_container);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
@@ -268,7 +269,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass, const void *dat
sc->valid_cpu_types = valid_cpu_types;
sc->silicon_rev = AST2700_A1_SILICON_REV;
- sc->sram_size = AST2700_TSP_RAM_SIZE;
sc->spis_num = 0;
sc->ehcis_num = 0;
sc->wdts_num = 0;
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 06/21] hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device realization order
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (4 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 05/21] hw/arm/aspeed_ast27x0-tsp: Switch TSP " Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-09-02 7:47 ` [SPAM] " Cédric Le Goater
2025-07-17 3:40 ` [PATCH v1 07/21] hw/arm/ast27x0: Add SRAM alias for TSP " Jamin Lin via
` (15 subsequent siblings)
21 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
AST2700 has a 128KB SRAM, physically mapped at 0x10000000–0x1001FFFF for the
main CA35 processor. The SSP coprocessor accesses this same memory at a
different memory address: 0x70000000–0x7001FFFF.
To support this shared memory model, this commit introduces "ssp.sram_mr_alias",
a "MemoryRegion" alias of the original SRAM region ("s->sram"). The alias is
realized during SSP SoC setup and mapped into the SSP's SoC memory map.
Additionally, because the SRAM must be realized before the SSP can create an
alias to it, the device realization order is explicitly managed:
"aspeed_soc_ast2700_ssp_realize()" is invoked after SRAM is initialized.
This ensures that SSP’s access to shared SRAM functions correctly.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed_ast27x0-ssp.c | 5 +++++
hw/arm/aspeed_ast27x0.c | 15 ++++++++++++++-
3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 3dd317cfee..9b935b9bca 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -134,6 +134,7 @@ struct Aspeed27x0SSPSoCState {
UnimplementedDeviceState ipc[2];
UnimplementedDeviceState scuio;
MemoryRegion memory;
+ MemoryRegion sram_mr_alias;
ARMv7MState armv7m;
};
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 9641e27de1..b7b886f4bf 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -19,6 +19,7 @@
static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
+ [ASPEED_DEV_SRAM] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
@@ -192,6 +193,10 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
sc->memmap[ASPEED_DEV_SDRAM],
&s->dram_container);
+ /* SRAM */
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
+ &a->sram_mr_alias);
+
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 665627f788..9064249bed 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -624,6 +624,7 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
{
Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
+ MemoryRegion *mr;
Clock *sysclk;
sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
@@ -637,6 +638,9 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
return false;
}
+ mr = &s->sram;
+ memory_region_init_alias(&a->ssp.sram_mr_alias, OBJECT(s), "ssp.sram.alias",
+ mr, 0, memory_region_size(mr));
if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
return false;
}
@@ -779,7 +783,16 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
sc->memmap[ASPEED_DEV_SCUIO]);
- /* Coprocessors */
+ /*
+ * Coprocessors must be realized after the SRAM region.
+ *
+ * The SRAM is used for shared memory between the main CPU (PSP) and
+ * coprocessors. The coprocessors accesses this shared SRAM region
+ * through a memory alias mapped to a different physical address.
+ *
+ * Therefore, the SRAM must be fully initialized before the coprocessors
+ * can create aliases pointing to it.
+ */
if (mc->default_cpus > sc->num_cpus) {
if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
return;
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 06/21] hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device realization order
2025-07-17 3:40 ` [PATCH v1 06/21] hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device realization order Jamin Lin via
@ 2025-09-02 7:47 ` Cédric Le Goater
2025-09-03 1:48 ` Jamin Lin
0 siblings, 1 reply; 61+ messages in thread
From: Cédric Le Goater @ 2025-09-02 7:47 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 7/17/25 05:40, Jamin Lin wrote:
> AST2700 has a 128KB SRAM, physically mapped at 0x10000000–0x1001FFFF for the
> main CA35 processor. The SSP coprocessor accesses this same memory at a
> different memory address: 0x70000000–0x7001FFFF.
>
> To support this shared memory model, this commit introduces "ssp.sram_mr_alias",
> a "MemoryRegion" alias of the original SRAM region ("s->sram"). The alias is
> realized during SSP SoC setup and mapped into the SSP's SoC memory map.
>
> Additionally, because the SRAM must be realized before the SSP can create an
> alias to it, the device realization order is explicitly managed:
> "aspeed_soc_ast2700_ssp_realize()" is invoked after SRAM is initialized.
>
> This ensures that SSP’s access to shared SRAM functions correctly.
Could the 'sram' MemoryRegion of main SoC be passed to the coprocessors
using a property ? Like done for dram. This would be simpler I think.
Thanks,
C.
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> include/hw/arm/aspeed_soc.h | 1 +
> hw/arm/aspeed_ast27x0-ssp.c | 5 +++++
> hw/arm/aspeed_ast27x0.c | 15 ++++++++++++++-
> 3 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 3dd317cfee..9b935b9bca 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -134,6 +134,7 @@ struct Aspeed27x0SSPSoCState {
> UnimplementedDeviceState ipc[2];
> UnimplementedDeviceState scuio;
> MemoryRegion memory;
> + MemoryRegion sram_mr_alias;
>
> ARMv7MState armv7m;
> };
> diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
> index 9641e27de1..b7b886f4bf 100644
> --- a/hw/arm/aspeed_ast27x0-ssp.c
> +++ b/hw/arm/aspeed_ast27x0-ssp.c
> @@ -19,6 +19,7 @@
>
> static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
> [ASPEED_DEV_SDRAM] = 0x00000000,
> + [ASPEED_DEV_SRAM] = 0x70000000,
> [ASPEED_DEV_INTC] = 0x72100000,
> [ASPEED_DEV_SCU] = 0x72C02000,
> [ASPEED_DEV_SCUIO] = 0x74C02000,
> @@ -192,6 +193,10 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
> sc->memmap[ASPEED_DEV_SDRAM],
> &s->dram_container);
>
> + /* SRAM */
> + memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
> + &a->sram_mr_alias);
> +
> /* SCU */
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
> return;
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 665627f788..9064249bed 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -624,6 +624,7 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
> {
> Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
> AspeedSoCState *s = ASPEED_SOC(dev);
> + MemoryRegion *mr;
> Clock *sysclk;
>
> sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
> @@ -637,6 +638,9 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
> return false;
> }
>
> + mr = &s->sram;
> + memory_region_init_alias(&a->ssp.sram_mr_alias, OBJECT(s), "ssp.sram.alias",
> + mr, 0, memory_region_size(mr));
> if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
> return false;
> }
> @@ -779,7 +783,16 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
> sc->memmap[ASPEED_DEV_SCUIO]);
>
> - /* Coprocessors */
> + /*
> + * Coprocessors must be realized after the SRAM region.
> + *
> + * The SRAM is used for shared memory between the main CPU (PSP) and
> + * coprocessors. The coprocessors accesses this shared SRAM region
> + * through a memory alias mapped to a different physical address.
> + *
> + * Therefore, the SRAM must be fully initialized before the coprocessors
> + * can create aliases pointing to it.
> + */
> if (mc->default_cpus > sc->num_cpus) {
> if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
> return;
^ permalink raw reply [flat|nested] 61+ messages in thread* RE: [SPAM] [PATCH v1 06/21] hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device realization order
2025-09-02 7:47 ` [SPAM] " Cédric Le Goater
@ 2025-09-03 1:48 ` Jamin Lin
0 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin @ 2025-09-03 1:48 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric
> Subject: Re: [SPAM] [PATCH v1 06/21] hw/arm/ast27x0: Add SRAM alias for SSP
> and ensure correct device realization order
>
> On 7/17/25 05:40, Jamin Lin wrote:
> > AST2700 has a 128KB SRAM, physically mapped at 0x10000000–0x1001FFFF
> > for the main CA35 processor. The SSP coprocessor accesses this same
> > memory at a different memory address: 0x70000000–0x7001FFFF.
> >
> > To support this shared memory model, this commit introduces
> > "ssp.sram_mr_alias", a "MemoryRegion" alias of the original SRAM
> > region ("s->sram"). The alias is realized during SSP SoC setup and mapped
> into the SSP's SoC memory map.
> >
> > Additionally, because the SRAM must be realized before the SSP can
> > create an alias to it, the device realization order is explicitly managed:
> > "aspeed_soc_ast2700_ssp_realize()" is invoked after SRAM is initialized.
> >
> > This ensures that SSP’s access to shared SRAM functions correctly.
>
> Could the 'sram' MemoryRegion of main SoC be passed to the coprocessors
> using a property ? Like done for dram. This would be simpler I think.
>
Will do.
Thanks for your review and suggestion.
Jamin
> Thanks,
>
> C.
>
>
>
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > include/hw/arm/aspeed_soc.h | 1 +
> > hw/arm/aspeed_ast27x0-ssp.c | 5 +++++
> > hw/arm/aspeed_ast27x0.c | 15 ++++++++++++++-
> > 3 files changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> > index 3dd317cfee..9b935b9bca 100644
> > --- a/include/hw/arm/aspeed_soc.h
> > +++ b/include/hw/arm/aspeed_soc.h
> > @@ -134,6 +134,7 @@ struct Aspeed27x0SSPSoCState {
> > UnimplementedDeviceState ipc[2];
> > UnimplementedDeviceState scuio;
> > MemoryRegion memory;
> > + MemoryRegion sram_mr_alias;
> >
> > ARMv7MState armv7m;
> > };
> > diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
> > index 9641e27de1..b7b886f4bf 100644
> > --- a/hw/arm/aspeed_ast27x0-ssp.c
> > +++ b/hw/arm/aspeed_ast27x0-ssp.c
> > @@ -19,6 +19,7 @@
> >
> > static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
> > [ASPEED_DEV_SDRAM] = 0x00000000,
> > + [ASPEED_DEV_SRAM] = 0x70000000,
> > [ASPEED_DEV_INTC] = 0x72100000,
> > [ASPEED_DEV_SCU] = 0x72C02000,
> > [ASPEED_DEV_SCUIO] = 0x74C02000,
> > @@ -192,6 +193,10 @@ static void
> aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
> >
> sc->memmap[ASPEED_DEV_SDRAM],
> > &s->dram_container);
> >
> > + /* SRAM */
> > + memory_region_add_subregion(s->memory,
> sc->memmap[ASPEED_DEV_SRAM],
> > + &a->sram_mr_alias);
> > +
> > /* SCU */
> > if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
> > return;
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
> > 665627f788..9064249bed 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -624,6 +624,7 @@ static bool
> aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
> > {
> > Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
> > AspeedSoCState *s = ASPEED_SOC(dev);
> > + MemoryRegion *mr;
> > Clock *sysclk;
> >
> > sysclk = clock_new(OBJECT(s), "SSP_SYSCLK"); @@ -637,6 +638,9
> @@
> > static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
> > return false;
> > }
> >
> > + mr = &s->sram;
> > + memory_region_init_alias(&a->ssp.sram_mr_alias, OBJECT(s),
> "ssp.sram.alias",
> > + mr, 0, memory_region_size(mr));
> > if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
> > return false;
> > }
> > @@ -779,7 +783,16 @@ static void
> aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> > aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
> > sc->memmap[ASPEED_DEV_SCUIO]);
> >
> > - /* Coprocessors */
> > + /*
> > + * Coprocessors must be realized after the SRAM region.
> > + *
> > + * The SRAM is used for shared memory between the main CPU (PSP)
> and
> > + * coprocessors. The coprocessors accesses this shared SRAM region
> > + * through a memory alias mapped to a different physical address.
> > + *
> > + * Therefore, the SRAM must be fully initialized before the
> coprocessors
> > + * can create aliases pointing to it.
> > + */
> > if (mc->default_cpus > sc->num_cpus) {
> > if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
> > return;
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v1 07/21] hw/arm/ast27x0: Add SRAM alias for TSP and ensure correct device realization order
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (5 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 06/21] hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device realization order Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP " Jamin Lin via
` (14 subsequent siblings)
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
AST2700 has a 128KB SRAM, physically mapped at 0x10000000–0x1001FFFF for the
main CA35 processor. The TSP coprocessor accesses this same memory at a
different memory address: 0x70000000–0x7001FFFF.
To support this shared memory model, this commit introduces "tsp.sram_mr_alias",
a "MemoryRegion" alias of the original SRAM region ("s->sram"). The alias is
realized during TSP SoC setup and mapped into the TSP's SoC memory map.
Additionally, because the SRAM must be realized before the TSP can create an
alias to it, the device realization order is explicitly managed:
"aspeed_soc_ast2700_tsp_realize()" is invoked after SRAM is initialized.
This ensures that TSP’s access to shared SRAM functions correctly.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed_ast27x0-tsp.c | 5 +++++
hw/arm/aspeed_ast27x0.c | 4 ++++
3 files changed, 10 insertions(+)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 9b935b9bca..1e4f8580b1 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -148,6 +148,7 @@ struct Aspeed27x0TSPSoCState {
UnimplementedDeviceState ipc[2];
UnimplementedDeviceState scuio;
MemoryRegion memory;
+ MemoryRegion sram_mr_alias;
ARMv7MState armv7m;
};
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index a70e30fc16..8438aefee5 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -19,6 +19,7 @@
static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
+ [ASPEED_DEV_SRAM] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
@@ -192,6 +193,10 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
sc->memmap[ASPEED_DEV_SDRAM],
&s->dram_container);
+ /* SRAM */
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
+ &a->sram_mr_alias);
+
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 9064249bed..8272a28ad5 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -652,6 +652,7 @@ static bool aspeed_soc_ast2700_tsp_realize(DeviceState *dev, Error **errp)
{
Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
+ MemoryRegion *mr;
Clock *sysclk;
sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
@@ -665,6 +666,9 @@ static bool aspeed_soc_ast2700_tsp_realize(DeviceState *dev, Error **errp)
return false;
}
+ mr = &s->sram;
+ memory_region_init_alias(&a->tsp.sram_mr_alias, OBJECT(s), "tsp.sram.alias",
+ mr, 0, memory_region_size(mr));
if (!qdev_realize(DEVICE(&a->tsp), NULL, &error_abort)) {
return false;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (6 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 07/21] hw/arm/ast27x0: Add SRAM alias for TSP " Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-09-02 8:09 ` [SPAM] " Cédric Le Goater
2025-07-17 3:40 ` [PATCH v1 09/21] hw/arm/ast27x0: Add SCU alias for TSP " Jamin Lin via
` (13 subsequent siblings)
21 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
AST2700 has a single SCU hardware block, memory-mapped at 0x12C02000–0x12C03FFF
from the perspective of the main CA35 processor (PSP). The SSP coprocessor accesses
this same SCU block at a different address: 0x72C02000–0x72C03FFF.
To support this shared SCU model, this commit introduces "ssp.scu_mr_alias",
a "MemoryRegion" alias of the original SCU region ("s->scu.iomem"). The alias is
realized during SSP SoC setup and mapped into the SSP's SoC memory map.
Additionally, because the SCU must be realized before the SSP can create an alias
to it, the device realization order is explicitly managed:
"aspeed_soc_ast2700_ssp_realize()" is invoked after the SCU is initialized.
This ensures that PSP and SSP access a consistent SCU state, as expected by hardware.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed_ast27x0-ssp.c | 9 ++-------
hw/arm/aspeed_ast27x0.c | 24 ++++++++++++++++++------
3 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 1e4f8580b1..65a452123b 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -135,6 +135,7 @@ struct Aspeed27x0SSPSoCState {
UnimplementedDeviceState scuio;
MemoryRegion memory;
MemoryRegion sram_mr_alias;
+ MemoryRegion scu_mr_alias;
ARMv7MState armv7m;
};
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index b7b886f4bf..0a58b8ea4b 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -135,9 +135,7 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
int i;
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
- object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
- qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
for (i = 0; i < sc->uarts_num; i++) {
object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
@@ -198,10 +196,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
&a->sram_mr_alias);
/* SCU */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
+ &a->scu_mr_alias);
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
@@ -273,7 +269,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass, const void *dat
dc->realize = aspeed_soc_ast27x0ssp_realize;
sc->valid_cpu_types = valid_cpu_types;
- sc->silicon_rev = AST2700_A1_SILICON_REV;
sc->spis_num = 0;
sc->ehcis_num = 0;
sc->wdts_num = 0;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 8272a28ad5..04b8b340ba 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -641,6 +641,10 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
mr = &s->sram;
memory_region_init_alias(&a->ssp.sram_mr_alias, OBJECT(s), "ssp.sram.alias",
mr, 0, memory_region_size(mr));
+
+ mr = &s->scu.iomem;
+ memory_region_init_alias(&a->ssp.scu_mr_alias, OBJECT(s), "ssp.scu.alias",
+ mr, 0, memory_region_size(mr));
if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
return false;
}
@@ -788,14 +792,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_SCUIO]);
/*
- * Coprocessors must be realized after the SRAM region.
+ * Coprocessors must be realized after the SRAM and SCU regions.
+ *
+ * The SRAM is used as shared memory between the main CPU (PSP) and the
+ * coprocessors. Coprocessors access this shared SRAM region through a
+ * MemoryRegion alias mapped to a different physical address.
+ *
+ * Similarly, the SCU is a single hardware block shared across all
+ * processors. Coprocessors access it via a MemoryRegion alias that maps
+ * to a different address than the one used by the main CPU.
*
- * The SRAM is used for shared memory between the main CPU (PSP) and
- * coprocessors. The coprocessors accesses this shared SRAM region
- * through a memory alias mapped to a different physical address.
+ * Therefore, both the SRAM and SCU must be fully initialized before the
+ * coprocessors can create aliases pointing to them.
*
- * Therefore, the SRAM must be fully initialized before the coprocessors
- * can create aliases pointing to it.
+ * To ensure correctness, the device realization order is explicitly
+ * managed:
+ * coprocessors are initialized only after SRAM and SCU are ready.
*/
if (mc->default_cpus > sc->num_cpus) {
if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order
2025-07-17 3:40 ` [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP " Jamin Lin via
@ 2025-09-02 8:09 ` Cédric Le Goater
2025-09-23 8:31 ` Jamin Lin
0 siblings, 1 reply; 61+ messages in thread
From: Cédric Le Goater @ 2025-09-02 8:09 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 7/17/25 05:40, Jamin Lin wrote:
> AST2700 has a single SCU hardware block, memory-mapped at 0x12C02000–0x12C03FFF
> from the perspective of the main CA35 processor (PSP). The SSP coprocessor accesses
> this same SCU block at a different address: 0x72C02000–0x72C03FFF.
>
> To support this shared SCU model, this commit introduces "ssp.scu_mr_alias",
> a "MemoryRegion" alias of the original SCU region ("s->scu.iomem"). The alias is
> realized during SSP SoC setup and mapped into the SSP's SoC memory map.
>
> Additionally, because the SCU must be realized before the SSP can create an alias
> to it, the device realization order is explicitly managed:
> "aspeed_soc_ast2700_ssp_realize()" is invoked after the SCU is initialized.
>
> This ensures that PSP and SSP access a consistent SCU state, as expected by hardware.
The SCU model of the main SoC could be passed as a link to the coprocessor
models, like done for the timer model. But the problem is elsewhere.
I think we need to rework the coprocessor models.
Currently, Aspeed27x0TSPSoCState and Aspeed27x0SSPSoCState inherit from
AspeedSoCState and looking at the aspeed_soc_ast27x0{t,s}sp_init handlers,
it seems clear that AspeedSoCState has too much state. We need a simplified
version of AspeedSoCState for the coprocessors.
Please rethink the proposal with that in mind.
Thanks,
C.
^ permalink raw reply [flat|nested] 61+ messages in thread* RE: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order
2025-09-02 8:09 ` [SPAM] " Cédric Le Goater
@ 2025-09-23 8:31 ` Jamin Lin
2025-09-23 11:33 ` Cédric Le Goater
0 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin @ 2025-09-23 8:31 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric
> Subject: Re: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP
> and ensure correct device realization order
>
> On 7/17/25 05:40, Jamin Lin wrote:
> > AST2700 has a single SCU hardware block, memory-mapped at
> > 0x12C02000–0x12C03FFF from the perspective of the main CA35 processor
> > (PSP). The SSP coprocessor accesses this same SCU block at a different
> address: 0x72C02000–0x72C03FFF.
> >
> > To support this shared SCU model, this commit introduces
> > "ssp.scu_mr_alias", a "MemoryRegion" alias of the original SCU region
> > ("s->scu.iomem"). The alias is realized during SSP SoC setup and mapped into
> the SSP's SoC memory map.
> >
> > Additionally, because the SCU must be realized before the SSP can
> > create an alias to it, the device realization order is explicitly managed:
> > "aspeed_soc_ast2700_ssp_realize()" is invoked after the SCU is initialized.
> >
> > This ensures that PSP and SSP access a consistent SCU state, as expected by
> hardware.
>
> The SCU model of the main SoC could be passed as a link to the coprocessor
> models, like done for the timer model. But the problem is elsewhere.
> I think we need to rework the coprocessor models.
>
> Currently, Aspeed27x0TSPSoCState and Aspeed27x0SSPSoCState inherit from
> AspeedSoCState and looking at the aspeed_soc_ast27x0{t,s}sp_init handlers, it
> seems clear that AspeedSoCState has too much state. We need a simplified
> version of AspeedSoCState for the coprocessors.
>
> Please rethink the proposal with that in mind.
>
This rework is quite large. To make review easier and avoid an oversized series, I plan to split it into 3 separate patch series:
Series A
1. Move the boot ROM helper from aspeed.c to aspeed_soc_common.c and declare it in aspeed_soc.h, so all ASPEED boards can reuse it.
2. Support vbootrom with coprocessor.
Series B
3. Migrate all ASPEED coprocessors (e.g. SSP/TSP) to a common AspeedCoprocessorState.
Series C
4. Introduce an FC SoC class.
5. Refactor SSP/TSP to share common controllers (e.g. SRAM/SCU) with PSP.
6. Gate SSP/TSP CPU power via the SCU
Thanks-Jamin
> Thanks,
>
> C.
>
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order
2025-09-23 8:31 ` Jamin Lin
@ 2025-09-23 11:33 ` Cédric Le Goater
2025-09-24 6:03 ` Jamin Lin
0 siblings, 1 reply; 61+ messages in thread
From: Cédric Le Goater @ 2025-09-23 11:33 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hello Jamin,
On 9/23/25 10:31, Jamin Lin wrote:
> Hi Cédric
>
>> Subject: Re: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP
>> and ensure correct device realization order
>>
>> On 7/17/25 05:40, Jamin Lin wrote:
>>> AST2700 has a single SCU hardware block, memory-mapped at
>>> 0x12C02000–0x12C03FFF from the perspective of the main CA35 processor
>>> (PSP). The SSP coprocessor accesses this same SCU block at a different
>> address: 0x72C02000–0x72C03FFF.
>>>
>>> To support this shared SCU model, this commit introduces
>>> "ssp.scu_mr_alias", a "MemoryRegion" alias of the original SCU region
>>> ("s->scu.iomem"). The alias is realized during SSP SoC setup and mapped into
>> the SSP's SoC memory map.
>>>
>>> Additionally, because the SCU must be realized before the SSP can
>>> create an alias to it, the device realization order is explicitly managed:
>>> "aspeed_soc_ast2700_ssp_realize()" is invoked after the SCU is initialized.
>>>
>>> This ensures that PSP and SSP access a consistent SCU state, as expected by
>> hardware.
>>
>> The SCU model of the main SoC could be passed as a link to the coprocessor
>> models, like done for the timer model. But the problem is elsewhere.
>> I think we need to rework the coprocessor models.
>>
>> Currently, Aspeed27x0TSPSoCState and Aspeed27x0SSPSoCState inherit from
>> AspeedSoCState and looking at the aspeed_soc_ast27x0{t,s}sp_init handlers, it
>> seems clear that AspeedSoCState has too much state. We need a simplified
>> version of AspeedSoCState for the coprocessors.
>>
>> Please rethink the proposal with that in mind.
>>
> This rework is quite large. To make review easier and avoid an oversized series, I plan to split it into 3 separate patch series:
>
> Series A
> 1. Move the boot ROM helper from aspeed.c to aspeed_soc_common.c and declare it in aspeed_soc.h, so all ASPEED boards can reuse it.
> 2. Support vbootrom with coprocessor.
This should be quickly merged.
>
> Series B
> 3. Migrate all ASPEED coprocessors (e.g. SSP/TSP) to a common AspeedCoprocessorState.
Is 'AspeedCoprocessorState' a new model structure minimizing the number
of sub controllers ? if so, looks good. Could be merged fairly quickly.
> Series C
> 4. Introduce an FC SoC class.
> 5. Refactor SSP/TSP to share common controllers (e.g. SRAM/SCU) with PSP.
> 6. Gate SSP/TSP CPU power via the SCU
OK That's the long term goal. Let's plan it for QEMU 10.2.
Thanks,
C.
^ permalink raw reply [flat|nested] 61+ messages in thread* RE: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order
2025-09-23 11:33 ` Cédric Le Goater
@ 2025-09-24 6:03 ` Jamin Lin
2025-09-24 11:13 ` Cédric Le Goater
0 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin @ 2025-09-24 6:03 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric
> Subject: Re: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP
> and ensure correct device realization order
>
> Hello Jamin,
>
> On 9/23/25 10:31, Jamin Lin wrote:
> > Hi Cédric
> >
> >> Subject: Re: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias
> >> for SSP and ensure correct device realization order
> >>
> >> On 7/17/25 05:40, Jamin Lin wrote:
> >>> AST2700 has a single SCU hardware block, memory-mapped at
> >>> 0x12C02000–0x12C03FFF from the perspective of the main CA35
> >>> processor (PSP). The SSP coprocessor accesses this same SCU block at
> >>> a different
> >> address: 0x72C02000–0x72C03FFF.
> >>>
> >>> To support this shared SCU model, this commit introduces
> >>> "ssp.scu_mr_alias", a "MemoryRegion" alias of the original SCU
> >>> region ("s->scu.iomem"). The alias is realized during SSP SoC setup
> >>> and mapped into
> >> the SSP's SoC memory map.
> >>>
> >>> Additionally, because the SCU must be realized before the SSP can
> >>> create an alias to it, the device realization order is explicitly managed:
> >>> "aspeed_soc_ast2700_ssp_realize()" is invoked after the SCU is initialized.
> >>>
> >>> This ensures that PSP and SSP access a consistent SCU state, as
> >>> expected by
> >> hardware.
> >>
> >> The SCU model of the main SoC could be passed as a link to the
> >> coprocessor models, like done for the timer model. But the problem is
> elsewhere.
> >> I think we need to rework the coprocessor models.
> >>
> >> Currently, Aspeed27x0TSPSoCState and Aspeed27x0SSPSoCState inherit
> >> from AspeedSoCState and looking at the aspeed_soc_ast27x0{t,s}sp_init
> >> handlers, it seems clear that AspeedSoCState has too much state. We
> >> need a simplified version of AspeedSoCState for the coprocessors.
> >>
> >> Please rethink the proposal with that in mind.
> >>
> > This rework is quite large. To make review easier and avoid an oversized
> series, I plan to split it into 3 separate patch series:
> >
> > Series A
> > 1. Move the boot ROM helper from aspeed.c to aspeed_soc_common.c and
> declare it in aspeed_soc.h, so all ASPEED boards can reuse it.
> > 2. Support vbootrom with coprocessor.
>
> This should be quickly merged.
>
> >
> > Series B
> > 3. Migrate all ASPEED coprocessors (e.g. SSP/TSP) to a common
> AspeedCoprocessorState.
>
> Is 'AspeedCoprocessorState' a new model structure minimizing the number of
> sub controllers ? if so, looks good. Could be merged fairly quickly.
>
Yes, I am planning to use the new AspeedCoprocessorState instead of AspeedSoCState for SSP and TSP.
struct Aspeed27x0SSPSoCState {
AspeedSoCState parent; -------> Change to AspeedCoprocessorState
AspeedINTCState intc[2];
UnimplementedDeviceState ipc[2];
UnimplementedDeviceState scuio;
ARMv7MState armv7m;
};
struct Aspeed27x0TSPSoCState {
AspeedSoCState parent; -------> Change to AspeedCoprocessorState
AspeedINTCState intc[2];
UnimplementedDeviceState ipc[2];
UnimplementedDeviceState scuio;
ARMv7MState armv7m;
};
This change consolidates SSP and TSP under a common coprocessor model,
reducing duplication and aligning them with the new AspeedCoprocessorState abstraction.
Thanks-Jamin
> > Series C
> > 4. Introduce an FC SoC class.
> > 5. Refactor SSP/TSP to share common controllers (e.g. SRAM/SCU) with PSP.
> > 6. Gate SSP/TSP CPU power via the SCU
>
> OK That's the long term goal. Let's plan it for QEMU 10.2.
>
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order
2025-09-24 6:03 ` Jamin Lin
@ 2025-09-24 11:13 ` Cédric Le Goater
2025-09-25 2:32 ` Jamin Lin
0 siblings, 1 reply; 61+ messages in thread
From: Cédric Le Goater @ 2025-09-24 11:13 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hello Jamin,
>>> 3. Migrate all ASPEED coprocessors (e.g. SSP/TSP) to a common
>> AspeedCoprocessorState.
>>
>> Is 'AspeedCoprocessorState' a new model structure minimizing the number of
>> sub controllers ? if so, looks good. Could be merged fairly quickly.
>>
>
> Yes, I am planning to use the new AspeedCoprocessorState instead of AspeedSoCState for SSP and TSP.
> struct Aspeed27x0SSPSoCState {
> AspeedSoCState parent; -------> Change to AspeedCoprocessorState
> AspeedINTCState intc[2];
> UnimplementedDeviceState ipc[2];
> UnimplementedDeviceState scuio;
>
> ARMv7MState armv7m;
> };
>
> struct Aspeed27x0TSPSoCState {
> AspeedSoCState parent; -------> Change to AspeedCoprocessorState
> AspeedINTCState intc[2];
> UnimplementedDeviceState ipc[2];
> UnimplementedDeviceState scuio;
>
> ARMv7MState armv7m;
> };
> This change consolidates SSP and TSP under a common coprocessor model,
> reducing duplication and aligning them with the new AspeedCoprocessorState abstraction.
Aspeed27x0TSPSoCState and Aspeed27x0SSPSoCState look similar. Could they
be merged ?
Thanks,
C.
^ permalink raw reply [flat|nested] 61+ messages in thread* RE: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order
2025-09-24 11:13 ` Cédric Le Goater
@ 2025-09-25 2:32 ` Jamin Lin
2025-09-26 3:13 ` Jamin Lin
0 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin @ 2025-09-25 2:32 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric
> Subject: Re: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP
> and ensure correct device realization order
>
> Hello Jamin,
>
>
> >>> 3. Migrate all ASPEED coprocessors (e.g. SSP/TSP) to a common
> >> AspeedCoprocessorState.
> >>
> >> Is 'AspeedCoprocessorState' a new model structure minimizing the
> >> number of sub controllers ? if so, looks good. Could be merged fairly quickly.
> >>
> >
> > Yes, I am planning to use the new AspeedCoprocessorState instead of
> AspeedSoCState for SSP and TSP.
> > struct Aspeed27x0SSPSoCState {
> > AspeedSoCState parent; -------> Change to AspeedCoprocessorState
> > AspeedINTCState intc[2];
> > UnimplementedDeviceState ipc[2];
> > UnimplementedDeviceState scuio;
> >
> > ARMv7MState armv7m;
> > };
> >
> > struct Aspeed27x0TSPSoCState {
> > AspeedSoCState parent; -------> Change to AspeedCoprocessorState
> > AspeedINTCState intc[2];
> > UnimplementedDeviceState ipc[2];
> > UnimplementedDeviceState scuio;
> >
> > ARMv7MState armv7m;
> > };
> > This change consolidates SSP and TSP under a common coprocessor model,
> > reducing duplication and aligning them with the new
> AspeedCoprocessorState abstraction.
>
> Aspeed27x0TSPSoCState and Aspeed27x0SSPSoCState look similar. Could they
> be merged ?
>
Thanks for your suggestion.
Will try it.
Jamin
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 61+ messages in thread* RE: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order
2025-09-25 2:32 ` Jamin Lin
@ 2025-09-26 3:13 ` Jamin Lin
2025-09-26 7:44 ` Cédric Le Goater
0 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin @ 2025-09-26 3:13 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric
> > >>> 3. Migrate all ASPEED coprocessors (e.g. SSP/TSP) to a common
> > >> AspeedCoprocessorState.
> > >>
> > >> Is 'AspeedCoprocessorState' a new model structure minimizing the
> > >> number of sub controllers ? if so, looks good. Could be merged fairly
> quickly.
> > >>
> > >
> > > Yes, I am planning to use the new AspeedCoprocessorState instead of
> > AspeedSoCState for SSP and TSP.
> > > struct Aspeed27x0SSPSoCState {
> > > AspeedSoCState parent; -------> Change to AspeedCoprocessorState
> > > AspeedINTCState intc[2];
> > > UnimplementedDeviceState ipc[2];
> > > UnimplementedDeviceState scuio;
> > >
> > > ARMv7MState armv7m;
> > > };
> > >
> > > struct Aspeed27x0TSPSoCState {
> > > AspeedSoCState parent; -------> Change to AspeedCoprocessorState
> > > AspeedINTCState intc[2];
> > > UnimplementedDeviceState ipc[2];
> > > UnimplementedDeviceState scuio;
> > >
> > > ARMv7MState armv7m;
> > > };
> > > This change consolidates SSP and TSP under a common coprocessor
> > > model, reducing duplication and aligning them with the new
> > AspeedCoprocessorState abstraction.
> >
> > Aspeed27x0TSPSoCState and Aspeed27x0SSPSoCState look similar. Could
> > they be merged ?
> >
> Thanks for your suggestion.
> Will try it.
> Jamin
> > Thanks,
I am considering making the following APIs common so that both the Coprocessor and SoC can use them.
The Coprocessor state is AspeedCoprocessor
The general SoC state is AspeedSoC
A. MMIO Mapping
Currently:
void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
{
memory_region_add_subregion(s->memory, addr,
sysbus_mmio_get_region(dev, n));
}
void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
const char *name, hwaddr addr, uint64_t size)
{
qdev_prop_set_string(DEVICE(dev), "name", name);
qdev_prop_set_uint64(DEVICE(dev), "size", size);
sysbus_realize(dev, &error_abort);
memory_region_add_subregion_overlap(s->memory, addr,
sysbus_mmio_get_region(dev, 0), -1000);
}
Proposal:
Replace AspeedSoCState *s with MemoryRegion *memory.
This way, the functions can be reused for both AspeedSoC and AspeedCoprocessor.
void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n, hwaddr addr);
void aspeed_mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev,
const char *name, hwaddr addr, uint64_t size);
B. UART Index Helpers
Currently:
static inline int aspeed_uart_first(AspeedSoCClass *sc)
{
return aspeed_uart_index(sc->uarts_base);
}
static inline int aspeed_uart_last(AspeedSoCClass *sc)
{
return aspeed_uart_first(sc) + sc->uarts_num - 1;
}
Proposal:
Make them independent of AspeedSoCClass, so they can be reused:
static inline int aspeed_uart_first(int uarts_base);
static inline int aspeed_uart_last(int uarts_base, int uarts_num);
C. UART Realization
This case looks more complex. Possible approaches:
1. Create a new API specifically for the coprocessor.
2. Add extra parameters to the existing APIs instead of relying on AspeedSoCState.
For example, the current SoC UART realization is tightly bound to AspeedSoCState.
Making it generic would require additional parameters (such as the UART array, base index, memmap, and IRQ handler) so it could be reused by both SoC and Coprocessor.
Could you please give me any suggestion?
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
{
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
SerialMM *smm;
for (int i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
smm = &s->uart[i];
/* Chardev property is set by the machine. */
qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
return false;
}
sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
}
return true;
}
void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
{
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
int uart_first = aspeed_uart_first(sc);
int uart_index = aspeed_uart_index(dev);
int i = uart_index - uart_first;
g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
}
D. Common APIs in Multiple SoCs
The following APIs are already widely used across AST2400, AST2500, AST2600, AST2700, and AST1030 SoC realizations:
Are you agree if I create a new aspeed_coprocessor_cpu_type and aspeed_coprocessor_get_irq for Coprocessor?
Could you please give me any suggestion?
const char *aspeed_soc_cpu_type(AspeedSoCClass *sc)
{
assert(sc->valid_cpu_types);
assert(sc->valid_cpu_types[0]);
assert(!sc->valid_cpu_types[1]);
return sc->valid_cpu_types[0];
}
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
{
return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
}
Thanks-Jamin
> >
> > C.
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order
2025-09-26 3:13 ` Jamin Lin
@ 2025-09-26 7:44 ` Cédric Le Goater
0 siblings, 0 replies; 61+ messages in thread
From: Cédric Le Goater @ 2025-09-26 7:44 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hello Jamin,
On 9/26/25 05:13, Jamin Lin wrote:
> Hi Cédric
>
>>>>>> 3. Migrate all ASPEED coprocessors (e.g. SSP/TSP) to a common
>>>>> AspeedCoprocessorState.
>>>>>
>>>>> Is 'AspeedCoprocessorState' a new model structure minimizing the
>>>>> number of sub controllers ? if so, looks good. Could be merged fairly
>> quickly.
>>>>>
>>>>
>>>> Yes, I am planning to use the new AspeedCoprocessorState instead of
>>> AspeedSoCState for SSP and TSP.
>>>> struct Aspeed27x0SSPSoCState {
>>>> AspeedSoCState parent; -------> Change to AspeedCoprocessorState
>>>> AspeedINTCState intc[2];
>>>> UnimplementedDeviceState ipc[2];
>>>> UnimplementedDeviceState scuio;
>>>>
>>>> ARMv7MState armv7m;
>>>> };
>>>>
>>>> struct Aspeed27x0TSPSoCState {
>>>> AspeedSoCState parent; -------> Change to AspeedCoprocessorState
>>>> AspeedINTCState intc[2];
>>>> UnimplementedDeviceState ipc[2];
>>>> UnimplementedDeviceState scuio;
>>>>
>>>> ARMv7MState armv7m;
>>>> };
>>>> This change consolidates SSP and TSP under a common coprocessor
>>>> model, reducing duplication and aligning them with the new
>>> AspeedCoprocessorState abstraction.
>>>
>>> Aspeed27x0TSPSoCState and Aspeed27x0SSPSoCState look similar. Could
>>> they be merged ?
>>>
>> Thanks for your suggestion.
>> Will try it.
>> Jamin
>>> Thanks,
>
> I am considering making the following APIs common so that both the Coprocessor and SoC can use them.
>
> The Coprocessor state is AspeedCoprocessor
> The general SoC state is AspeedSoC
Yes. If you need a base class to maintain common routines, you could
introduce a parent too.
For rest, please send patches. I rather discuss on a proposal than on
an unrelated email.
Thanks,
C.
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v1 09/21] hw/arm/ast27x0: Add SCU alias for TSP and ensure correct device realization order
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (7 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP " Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 10/21] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing Jamin Lin via
` (12 subsequent siblings)
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
AST2700 has a single SCU hardware block, memory-mapped at 0x12C02000–0x12C03FFF
from the perspective of the main CA35 processor (PSP). The TSP coprocessor accesses
this same SCU block at a different address: 0x72C02000–0x72C03FFF.
To support this shared SCU model, this commit introduces "tsp.scu_mr_alias",
a "MemoryRegion" alias of the original SCU region ("s->scu.iomem"). The alias is
realized during TSP SoC setup and mapped into the TSP's SoC memory map.
Additionally, because the SCU must be realized before the TSP can create an alias
to it, the device realization order is explicitly managed:
"aspeed_soc_ast2700_tsp_realize()" is invoked after the SCU is initialized.
This ensures that PSP and TSP access a consistent SCU state, as expected by hardware.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed_ast27x0-tsp.c | 9 ++-------
hw/arm/aspeed_ast27x0.c | 4 ++++
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 65a452123b..4152fbf495 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -150,6 +150,7 @@ struct Aspeed27x0TSPSoCState {
UnimplementedDeviceState scuio;
MemoryRegion memory;
MemoryRegion sram_mr_alias;
+ MemoryRegion scu_mr_alias;
ARMv7MState armv7m;
};
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 8438aefee5..6b035e2612 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -135,9 +135,7 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
int i;
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
- object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
- qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
for (i = 0; i < sc->uarts_num; i++) {
object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
@@ -198,10 +196,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
&a->sram_mr_alias);
/* SCU */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
+ &a->scu_mr_alias);
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
@@ -273,7 +269,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass, const void *dat
dc->realize = aspeed_soc_ast27x0tsp_realize;
sc->valid_cpu_types = valid_cpu_types;
- sc->silicon_rev = AST2700_A1_SILICON_REV;
sc->spis_num = 0;
sc->ehcis_num = 0;
sc->wdts_num = 0;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 04b8b340ba..2d27eb1deb 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -673,6 +673,10 @@ static bool aspeed_soc_ast2700_tsp_realize(DeviceState *dev, Error **errp)
mr = &s->sram;
memory_region_init_alias(&a->tsp.sram_mr_alias, OBJECT(s), "tsp.sram.alias",
mr, 0, memory_region_size(mr));
+
+ mr = &s->scu.iomem;
+ memory_region_init_alias(&a->tsp.scu_mr_alias, OBJECT(s), "tsp.scu.alias",
+ mr, 0, memory_region_size(mr));
if (!qdev_realize(DEVICE(&a->tsp), NULL, &error_abort)) {
return false;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 10/21] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (8 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 09/21] hw/arm/ast27x0: Add SCU alias for TSP " Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-09-02 7:51 ` [SPAM] " Cédric Le Goater
2025-07-17 3:40 ` [PATCH v1 11/21] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap and update realization order Jamin Lin via
` (11 subsequent siblings)
21 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
To support DRAM aliasing for coprocessors (SSP/TSP), this commit moves the
initialization of the SDMC (SDRAM controller) and DRAM models earlier in
the device realization order.
In the upcoming changes, the PSP will expose a portion of its DRAM as shared
memory by creating a memory region alias at a specific offset. This alias is
mapped into the coprocessor's SDRAM address space, allowing both PSP and the
coprocessor (SSP/TSP) to access the same physical memory through their respective
views — PSP via its DRAM, and the coprocessor via its SDRAM.
The remapping is configured through SCU registers and enables shared memory
communication between PSP and the coprocessors.
Therefore, the DRAM and SDMC devices must be realized before:
- the SCU, which configures the alias offset and size
- the coprocessors, which access the alias through their SDRAM window
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 2d27eb1deb..9d67c5f631 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -765,6 +765,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
+ /*
+ * SDMC - SDRAM Memory Controller
+ * The SDMC controller is unlocked at SPL stage.
+ * At present, only supports to emulate booting
+ * start from u-boot stage. Set SDMC controller
+ * unlocked by default. It is a temporarily solution.
+ */
+ object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
+ sc->memmap[ASPEED_DEV_SDMC]);
+
+ /* RAM */
+ if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
+ return;
+ }
+
/* SRAM */
name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size,
@@ -872,26 +892,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
}
- /*
- * SDMC - SDRAM Memory Controller
- * The SDMC controller is unlocked at SPL stage.
- * At present, only supports to emulate booting
- * start from u-boot stage. Set SDMC controller
- * unlocked by default. It is a temporarily solution.
- */
- object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
- &error_abort);
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
- return;
- }
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
- sc->memmap[ASPEED_DEV_SDMC]);
-
- /* RAM */
- if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
- return;
- }
-
/* Net */
for (i = 0; i < sc->macs_num; i++) {
object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 10/21] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing
2025-07-17 3:40 ` [PATCH v1 10/21] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing Jamin Lin via
@ 2025-09-02 7:51 ` Cédric Le Goater
2025-09-03 1:50 ` Jamin Lin
0 siblings, 1 reply; 61+ messages in thread
From: Cédric Le Goater @ 2025-09-02 7:51 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
On 7/17/25 05:40, Jamin Lin wrote:
> To support DRAM aliasing for coprocessors (SSP/TSP), this commit moves the
> initialization of the SDMC (SDRAM controller) and DRAM models earlier in
> the device realization order.
>
> In the upcoming changes, the PSP will expose a portion of its DRAM as shared
> memory by creating a memory region alias at a specific offset. This alias is
> mapped into the coprocessor's SDRAM address space, allowing both PSP and the
> coprocessor (SSP/TSP) to access the same physical memory through their respective
> views — PSP via its DRAM, and the coprocessor via its SDRAM.
>
> The remapping is configured through SCU registers and enables shared memory
> communication between PSP and the coprocessors.
>
> Therefore, the DRAM and SDMC devices must be realized before:
> - the SCU, which configures the alias offset and size
> - the coprocessors, which access the alias through their SDRAM window
>
> No functional change.
Please move this patch at the beginning of the series. It can be
merged early.
Thanks,
C.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> hw/arm/aspeed_ast27x0.c | 40 ++++++++++++++++++++--------------------
> 1 file changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index 2d27eb1deb..9d67c5f631 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -765,6 +765,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
> }
>
> + /*
> + * SDMC - SDRAM Memory Controller
> + * The SDMC controller is unlocked at SPL stage.
> + * At present, only supports to emulate booting
> + * start from u-boot stage. Set SDMC controller
> + * unlocked by default. It is a temporarily solution.
> + */
> + object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
> + &error_abort);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
> + return;
> + }
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
> + sc->memmap[ASPEED_DEV_SDMC]);
> +
> + /* RAM */
> + if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
> + return;
> + }
> +
> /* SRAM */
> name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index);
> if (!memory_region_init_ram(&s->sram, OBJECT(s), name, sc->sram_size,
> @@ -872,26 +892,6 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
> }
>
> - /*
> - * SDMC - SDRAM Memory Controller
> - * The SDMC controller is unlocked at SPL stage.
> - * At present, only supports to emulate booting
> - * start from u-boot stage. Set SDMC controller
> - * unlocked by default. It is a temporarily solution.
> - */
> - object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
> - &error_abort);
> - if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
> - return;
> - }
> - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
> - sc->memmap[ASPEED_DEV_SDMC]);
> -
> - /* RAM */
> - if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
> - return;
> - }
> -
> /* Net */
> for (i = 0; i < sc->macs_num; i++) {
> object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
^ permalink raw reply [flat|nested] 61+ messages in thread* RE: [SPAM] [PATCH v1 10/21] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing
2025-09-02 7:51 ` [SPAM] " Cédric Le Goater
@ 2025-09-03 1:50 ` Jamin Lin
0 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin @ 2025-09-03 1:50 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric
> Subject: Re: [SPAM] [PATCH v1 10/21] hw/arm/ast27x0: Move DRAM and
> SDMC initialization earlier to support memory aliasing
>
> On 7/17/25 05:40, Jamin Lin wrote:
> > To support DRAM aliasing for coprocessors (SSP/TSP), this commit moves
> > the initialization of the SDMC (SDRAM controller) and DRAM models
> > earlier in the device realization order.
> >
> > In the upcoming changes, the PSP will expose a portion of its DRAM as
> > shared memory by creating a memory region alias at a specific offset.
> > This alias is mapped into the coprocessor's SDRAM address space,
> > allowing both PSP and the coprocessor (SSP/TSP) to access the same
> > physical memory through their respective views — PSP via its DRAM, and the
> coprocessor via its SDRAM.
> >
> > The remapping is configured through SCU registers and enables shared
> > memory communication between PSP and the coprocessors.
> >
> > Therefore, the DRAM and SDMC devices must be realized before:
> > - the SCU, which configures the alias offset and size
> > - the coprocessors, which access the alias through their SDRAM
> > window
> >
> > No functional change.
>
> Please move this patch at the beginning of the series. It can be merged early.
>
Will do
Thanks for your review and suggestion.
Jamin
>
> Thanks,
>
> C.
>
>
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > hw/arm/aspeed_ast27x0.c | 40 ++++++++++++++++++++--------------------
> > 1 file changed, 20 insertions(+), 20 deletions(-)
> >
> > diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index
> > 2d27eb1deb..9d67c5f631 100644
> > --- a/hw/arm/aspeed_ast27x0.c
> > +++ b/hw/arm/aspeed_ast27x0.c
> > @@ -765,6 +765,26 @@ static void
> aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> >
> qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
> > }
> >
> > + /*
> > + * SDMC - SDRAM Memory Controller
> > + * The SDMC controller is unlocked at SPL stage.
> > + * At present, only supports to emulate booting
> > + * start from u-boot stage. Set SDMC controller
> > + * unlocked by default. It is a temporarily solution.
> > + */
> > + object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
> > + &error_abort);
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
> > + return;
> > + }
> > + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
> > + sc->memmap[ASPEED_DEV_SDMC]);
> > +
> > + /* RAM */
> > + if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
> > + return;
> > + }
> > +
> > /* SRAM */
> > name = g_strdup_printf("aspeed.sram.%d",
> CPU(&a->cpu[0])->cpu_index);
> > if (!memory_region_init_ram(&s->sram, OBJECT(s), name,
> > sc->sram_size, @@ -872,26 +892,6 @@ static void
> aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> > aspeed_soc_get_irq(s,
> ASPEED_DEV_EHCI1 + i));
> > }
> >
> > - /*
> > - * SDMC - SDRAM Memory Controller
> > - * The SDMC controller is unlocked at SPL stage.
> > - * At present, only supports to emulate booting
> > - * start from u-boot stage. Set SDMC controller
> > - * unlocked by default. It is a temporarily solution.
> > - */
> > - object_property_set_bool(OBJECT(&s->sdmc), "unlocked", true,
> > - &error_abort);
> > - if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
> > - return;
> > - }
> > - aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
> > - sc->memmap[ASPEED_DEV_SDMC]);
> > -
> > - /* RAM */
> > - if (!aspeed_soc_ast2700_dram_init(dev, errp)) {
> > - return;
> > - }
> > -
> > /* Net */
> > for (i = 0; i < sc->macs_num; i++) {
> > object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed",
> > true,
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v1 11/21] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap and update realization order
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (9 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 10/21] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 12/21] hw/arm/ast27x0: Add DRAM alias for TSP " Jamin Lin via
` (10 subsequent siblings)
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
This commit adds two MemoryRegion aliases to support PSP access to
SSP SDRAM through shared memory remapping, as defined by the default SCU
configuration.
The SSP coprocessor exposes two DRAM aliases:
- remap1 maps PSP DRAM at 0x400000000 (32MB) to SSP SDRAM offset 0x2000000
- remap2 maps PSP DRAM at 0x42c000000 (32MB) to SSP SDRAM offset 0x0
These regions correspond to the default SCU register values, which control
the mapping between PSP and coprocessor memory windows.
To ensure correctness, the aliases are initialized early in
aspeed_soc_ast2700_realize(), before SCU and coprocessor realization.
This allows SSP to reference the alias regions during its SDRAM setup.
Additionally, the realization order comment has been updated to reflect
the new DRAM dependency: coprocessors must now be realized after DRAM,
SRAM, and SCU are all initialized.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 2 ++
hw/arm/aspeed_ast27x0-ssp.c | 5 ++++
hw/arm/aspeed_ast27x0.c | 49 ++++++++++++++++++++++++++++---------
3 files changed, 45 insertions(+), 11 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 4152fbf495..d628a189c1 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -136,6 +136,8 @@ struct Aspeed27x0SSPSoCState {
MemoryRegion memory;
MemoryRegion sram_mr_alias;
MemoryRegion scu_mr_alias;
+ MemoryRegion sdram_remap1_alias;
+ MemoryRegion sdram_remap2_alias;
ARMv7MState armv7m;
};
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 0a58b8ea4b..fff95eac6a 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -187,6 +187,11 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
AST2700_SSP_SDRAM_SIZE, errp)) {
return;
}
+ /* SDRAM remap alias used by PSP to access SSP SDRAM */
+ memory_region_add_subregion(&s->dram_container, 0, &a->sdram_remap2_alias);
+ memory_region_add_subregion(&s->dram_container,
+ memory_region_size(&a->sdram_remap2_alias),
+ &a->sdram_remap1_alias);
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SDRAM],
&s->dram_container);
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 9d67c5f631..be130db5e2 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -803,6 +803,28 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom);
/* SCU */
+ /*
+ * The SSP coprocessor uses two memory aliases (remap1 and remap2)
+ * to access shared memory regions in the PSP DRAM:
+ *
+ * - remap1 maps PSP DRAM at 0x400000000 (size: 32MB) to SSP SDRAM
+ * offset 0x2000000
+ * - remap2 maps PSP DRAM at 0x42c000000 (size: 32MB) to SSP SDRAM
+ * offset 0x0
+ *
+ * These mappings correspond to the default values of the SCU registers:
+ *
+ * This configuration enables shared memory communication between the PSP
+ * and coprocessors, with address translation controlled by the SCU.
+ */
+ if (mc->default_cpus > sc->num_cpus) {
+ memory_region_init_alias(&a->ssp.sdram_remap1_alias, OBJECT(a),
+ "ssp.sdram.remap1", s->memory,
+ 0x400000000ULL, 32 * MiB);
+ memory_region_init_alias(&a->ssp.sdram_remap2_alias, OBJECT(a),
+ "ssp.sdram.remap2", s->memory,
+ 0x42c000000ULL, 32 * MiB);
+ }
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
}
@@ -816,22 +838,27 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_SCUIO]);
/*
- * Coprocessors must be realized after the SRAM and SCU regions.
+ * Coprocessors must be realized after the DRAM, SRAM, and SCU regions.
*
- * The SRAM is used as shared memory between the main CPU (PSP) and the
- * coprocessors. Coprocessors access this shared SRAM region through a
- * MemoryRegion alias mapped to a different physical address.
+ * - DRAM: Coprocessors access shared memory through MemoryRegion aliases
+ * that point into PSP's DRAM space. These aliases are mapped into the
+ * coprocessors' SDRAM windows at specific offsets (e.g., 0x0 and
+ * 0x2000000), and configured according to SCU register defaults.
+ * Therefore, DRAM must be fully initialized before coprocessors can
+ * attach aliases to it.
*
- * Similarly, the SCU is a single hardware block shared across all
- * processors. Coprocessors access it via a MemoryRegion alias that maps
- * to a different address than the one used by the main CPU.
+ * - SRAM: Used as shared memory between the PSP and coprocessors.
+ * Coprocessors access this memory via alias regions mapped to
+ * different physical addresses.
*
- * Therefore, both the SRAM and SCU must be fully initialized before the
- * coprocessors can create aliases pointing to them.
+ * - SCU: A single hardware block shared across all processors.
+ * Coprocessors access SCU registers through alias mappings.
+ * SCU must be initialized first to allow for consistent register
+ * state and memory remap configuration.
*
* To ensure correctness, the device realization order is explicitly
- * managed:
- * coprocessors are initialized only after SRAM and SCU are ready.
+ * managed: coprocessors are initialized only after DRAM, SRAM, and SCU
+ * are ready.
*/
if (mc->default_cpus > sc->num_cpus) {
if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 12/21] hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap and update realization order
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (10 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 11/21] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap and update realization order Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 13/21] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Jamin Lin via
` (9 subsequent siblings)
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
This commit adds a MemoryRegion alias to support PSP access to
TSP SDRAM through shared memory remapping, as defined by the default SCU
configuration.
The TSP coprocessor exposes one DRAM alias:
- remap maps PSP DRAM at 0x42e000000 (32MB) to TSP SDRAM offset 0x0
This region corresponds to the default SCU register value, which controls
the mapping between PSP and coprocessor memory windows.
To ensure correctness, the alias is initialized early in
aspeed_soc_ast2700_realize(), before SCU and coprocessor realization.
This allows TSP to reference the alias region during its SDRAM setup.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed_ast27x0-tsp.c | 2 ++
hw/arm/aspeed_ast27x0.c | 9 +++++++++
3 files changed, 12 insertions(+)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index d628a189c1..83e07582d2 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -153,6 +153,7 @@ struct Aspeed27x0TSPSoCState {
MemoryRegion memory;
MemoryRegion sram_mr_alias;
MemoryRegion scu_mr_alias;
+ MemoryRegion sdram_remap_alias;
ARMv7MState armv7m;
};
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 6b035e2612..4c3b18695e 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -187,6 +187,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
AST2700_TSP_SDRAM_SIZE, errp)) {
return;
}
+ /* SDRAM remap alias used by PSP to access TSP SDRAM */
+ memory_region_add_subregion(&s->dram_container, 0, &a->sdram_remap_alias);
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SDRAM],
&s->dram_container);
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index be130db5e2..0f988eaa4d 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -812,6 +812,12 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
* - remap2 maps PSP DRAM at 0x42c000000 (size: 32MB) to SSP SDRAM
* offset 0x0
*
+ * The TSP coprocessor uses one memory alias (remap) to access a shared
+ * region in the PSP DRAM:
+ *
+ * - remap maps PSP DRAM at 0x42e000000 (size: 32MB) to TSP SDRAM
+ * offset 0x0
+ *
* These mappings correspond to the default values of the SCU registers:
*
* This configuration enables shared memory communication between the PSP
@@ -824,6 +830,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
memory_region_init_alias(&a->ssp.sdram_remap2_alias, OBJECT(a),
"ssp.sdram.remap2", s->memory,
0x42c000000ULL, 32 * MiB);
+ memory_region_init_alias(&a->tsp.sdram_remap_alias, OBJECT(a),
+ "tsp.sdram.remap", s->memory,
+ 0x42e000000, 32 * MiB);
}
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 13/21] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (11 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 12/21] hw/arm/ast27x0: Add DRAM alias for TSP " Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 14/21] hw/arm/ast27x0: Start TSP " Jamin Lin via
` (8 subsequent siblings)
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
In the previous design, both the PSP and SSP were started together during
SoC initialization. However, on real hardware, the SSP begins in a powered-off
state. The typical boot sequence involves the PSP powering up first, loading
the SSP firmware binary into shared memory via DRAM remap, and then releasing
the SSP reset and enabling it through SCU control registers.
To more accurately model this behavior in QEMU, this commit sets the
"start-powered-off" property for the SSP's ARMv7M core. This change ensures
the SSP remains off until explicitly enabled via the SCU, simulating the
real-world flow where the PSP controls SSP boot through SCU interaction.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0-ssp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index fff95eac6a..b1dfbc4292 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -177,6 +177,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
+ /*
+ * The SSP starts in a powered-down state and can be powered up
+ * by setting the SSP Control Register through the SCU
+ * (System Control Unit)
+ */
+ object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
+ &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* SDRAM */
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 14/21] hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (12 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 13/21] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 15/21] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Jamin Lin via
` (7 subsequent siblings)
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
In the previous design, both the PSP and TSP were started together during
SoC initialization. However, on real hardware, the TSP begins in a powered-off
state. The typical boot sequence involves the PSP powering up first, loading
the TSP firmware binary into shared memory via DRAM remap, and then releasing
the TSP reset and enabling it through SCU control registers.
To more accurately model this behavior in QEMU, this commit sets the
"start-powered-off" property for the TSP's ARMv7M core. This change ensures
the TSP remains off until explicitly enabled via the SCU, simulating the
real-world flow where the PSP controls TSP boot through SCU interaction.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_ast27x0-tsp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 4c3b18695e..49a49604de 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -177,6 +177,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
object_property_set_link(OBJECT(&a->armv7m), "memory",
OBJECT(s->memory), &error_abort);
+ /*
+ * The TSP starts in a powered-down state and can be powered up
+ * by setting the TSP Control Register through the SCU
+ * (System Control Unit)
+ */
+ object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true,
+ &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
/* SDRAM */
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 15/21] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (13 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 14/21] hw/arm/ast27x0: Start TSP " Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 16/21] hw/misc/aspeed_scu: Add SCU support for TSP " Jamin Lin via
` (6 subsequent siblings)
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
This commit adds SCU register support for SSP SDRAM remap control and runtime
activation. It introduces logic for the PSP to dynamically configure the mapping
of its own DRAM windows into SSP-visible SDRAM space, enabling shared memory
communication via memory region aliases.
Two MemoryRegion aliases are attached to the SCU via QOM property links:
- ssp-sdram-remap1: maps PSP DRAM at 0x400000000 (size: 32MB) to SSP SDRAM
offset 0x2000000
- ssp-sdram-remap2: maps PSP DRAM at 0x42c000000 (size: 32MB) to SSP SDRAM
offset 0x0
The SCU registers AST2700_SCU_SSP_CTRL_1/2 and
AST2700_SCU_SSP_REMAP_ADDR_{1,2} / REMAP_SIZE_{1,2} allow runtime reconfiguration
of alias offset, base, and size.
Bumps the SCU VMState version to 3.
|------------------------------------------| |----------------------------|
| PSP DRAM | | SSP SDRAM |
|------------------------------------------| |----------------------------|
| 0x4_0000_0000 (SCU_124 << 4) | --> | 0x0000_0000 |
| remap1 base |---| | | - SCU_150: target addr |
| size: 32MB (SCU_14C) | | | | remap2 |
|------------------------------------------| | | |----------------------------|
| | | | | |
| 0x4_2C00_0000 (SCU_128 << 4) |-----| | 0x0200_0000 |
| remap2 base | | | - SCU_148: target addr |
| size: 32MB (SCU_154) | |---> | remap1 |
|------------------------------------------| |----------------------------|
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/misc/aspeed_scu.h | 3 ++
hw/arm/aspeed_ast27x0.c | 6 ++++
hw/misc/aspeed_scu.c | 53 ++++++++++++++++++++++++++++++++++--
3 files changed, 60 insertions(+), 2 deletions(-)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 684b48b722..408f821379 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -39,6 +39,9 @@ struct AspeedSCUState {
uint32_t hw_strap1;
uint32_t hw_strap2;
uint32_t hw_prot_key;
+
+ MemoryRegion *ssp_sdram_remap1;
+ MemoryRegion *ssp_sdram_remap2;
};
#define AST2400_A0_SILICON_REV 0x02000303U
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 0f988eaa4d..587c042c30 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -833,6 +833,12 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
memory_region_init_alias(&a->tsp.sdram_remap_alias, OBJECT(a),
"tsp.sdram.remap", s->memory,
0x42e000000, 32 * MiB);
+ object_property_set_link(OBJECT(&s->scu), "ssp-sdram-remap1",
+ OBJECT(&a->ssp.sdram_remap1_alias),
+ &error_abort);
+ object_property_set_link(OBJECT(&s->scu), "ssp-sdram-remap2",
+ OBJECT(&a->ssp.sdram_remap2_alias),
+ &error_abort);
}
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index a0ab5eed8f..df379cafbe 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -143,6 +143,14 @@
#define AST2700_HW_STRAP1_SEC2 TO_REG(0x28)
#define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C)
+/* SSP */
+#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124)
+#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128)
+#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148)
+#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14c)
+#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150)
+#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154)
+
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
#define AST2700_SCU_HPLL_EXT_PARAM TO_REG(0x304)
@@ -605,8 +613,8 @@ static void aspeed_scu_realize(DeviceState *dev, Error **errp)
static const VMStateDescription vmstate_aspeed_scu = {
.name = "aspeed.scu",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_AST2600_SCU_NR_REGS),
VMSTATE_END_OF_LIST()
@@ -618,6 +626,10 @@ static const Property aspeed_scu_properties[] = {
DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
+ DEFINE_PROP_LINK("ssp-sdram-remap1", AspeedSCUState, ssp_sdram_remap1,
+ TYPE_MEMORY_REGION, MemoryRegion *),
+ DEFINE_PROP_LINK("ssp-sdram-remap2", AspeedSCUState, ssp_sdram_remap2,
+ TYPE_MEMORY_REGION, MemoryRegion *),
};
static void aspeed_scu_class_init(ObjectClass *klass, const void *data)
@@ -902,6 +914,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
int reg = TO_REG(offset);
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
+ MemoryRegion *mr;
if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -913,6 +926,36 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
trace_aspeed_ast2700_scu_write(offset, size, data);
switch (reg) {
+ case AST2700_SCU_SSP_CTRL_1:
+ case AST2700_SCU_SSP_CTRL_2:
+ mr = (reg == AST2700_SCU_SSP_CTRL_1) ?
+ s->ssp_sdram_remap1 : s->ssp_sdram_remap2;
+ if (mr == NULL) {
+ return;
+ }
+ data &= 0x7fffffff;
+ memory_region_set_alias_offset(mr, (uint64_t) data << 4);
+ break;
+ case AST2700_SCU_SSP_REMAP_ADDR_1:
+ case AST2700_SCU_SSP_REMAP_ADDR_2:
+ mr = (reg == AST2700_SCU_SSP_REMAP_ADDR_1) ?
+ s->ssp_sdram_remap1 : s->ssp_sdram_remap2;
+ if (mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_set_address(mr, data);
+ break;
+ case AST2700_SCU_SSP_REMAP_SIZE_1:
+ case AST2700_SCU_SSP_REMAP_SIZE_2:
+ mr = (reg == AST2700_SCU_SSP_REMAP_SIZE_1) ?
+ s->ssp_sdram_remap1 : s->ssp_sdram_remap2;
+ if (mr == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_set_size(mr, data);
+ break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -940,6 +983,12 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC1] = 0x000000FF,
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
+ [AST2700_SCU_SSP_CTRL_1] = 0x40000000,
+ [AST2700_SCU_SSP_CTRL_2] = 0x42C00000,
+ [AST2700_SCU_SSP_REMAP_ADDR_1] = 0x02000000,
+ [AST2700_SCU_SSP_REMAP_SIZE_1] = 0x02000000,
+ [AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
+ [AST2700_SCU_SSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 16/21] hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (14 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 15/21] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 17/21] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Jamin Lin via
` (5 subsequent siblings)
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
This commit adds SCU register support for TSP SDRAM remap control and runtime
activation. Unlike SSP, the TSP does not support configurable target address remapping
through SCU registers. It only supports setting the PSP DRAM base and size, which
are then aliased into the TSP-visible SDRAM window.
One MemoryRegion alias is attached to the SCU via QOM property link:
- tsp-sdram-remap: maps PSP DRAM at 0x42E000000 (size: 32MB) to TSP SDRAM
offset 0x0
The SCU registers AST2700_SCU_TSP_CTRL_1 and
AST2700_SCU_TSP_REMAP_SIZE_2 allow runtime reconfiguration of the DRAM base (alias offset)
and mapping size.
|------------------------------------------| |----------------------------|
| PSP DRAM | | TSP SDRAM |
|------------------------------------------| |----------------------------|
| 0x42E0_0000_0 (SCU_168 << 4) | | 0x0000_0000 |
| remap base |------> | - fixed target addr |
| size: 32MB (SCU_194) | | |
|------------------------------------------| |----------------------------|
SCU VMState version remains at 3, as it was already bumped in a previous commit.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/misc/aspeed_scu.h | 1 +
hw/arm/aspeed_ast27x0.c | 3 +++
hw/misc/aspeed_scu.c | 24 +++++++++++++++++++++++-
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 408f821379..5e7c80feb1 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -42,6 +42,7 @@ struct AspeedSCUState {
MemoryRegion *ssp_sdram_remap1;
MemoryRegion *ssp_sdram_remap2;
+ MemoryRegion *tsp_sdram_remap;
};
#define AST2400_A0_SILICON_REV 0x02000303U
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 587c042c30..23096bda34 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -839,6 +839,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
object_property_set_link(OBJECT(&s->scu), "ssp-sdram-remap2",
OBJECT(&a->ssp.sdram_remap2_alias),
&error_abort);
+ object_property_set_link(OBJECT(&s->scu), "tsp-sdram-remap",
+ OBJECT(&a->tsp.sdram_remap_alias),
+ &error_abort);
}
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index df379cafbe..21a0d1ad5c 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -143,13 +143,15 @@
#define AST2700_HW_STRAP1_SEC2 TO_REG(0x28)
#define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C)
-/* SSP */
+/* SSP TSP */
#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124)
#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128)
#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148)
#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14c)
#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150)
#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154)
+#define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168)
+#define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194)
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
@@ -630,6 +632,8 @@ static const Property aspeed_scu_properties[] = {
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_LINK("ssp-sdram-remap2", AspeedSCUState, ssp_sdram_remap2,
TYPE_MEMORY_REGION, MemoryRegion *),
+ DEFINE_PROP_LINK("tsp-sdram-remap", AspeedSCUState, tsp_sdram_remap,
+ TYPE_MEMORY_REGION, MemoryRegion *),
};
static void aspeed_scu_class_init(ObjectClass *klass, const void *data)
@@ -956,6 +960,22 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
data &= 0x3fffffff;
memory_region_set_size(mr, data);
break;
+ case AST2700_SCU_TSP_CTRL_1:
+ if (s->tsp_sdram_remap == NULL) {
+ return;
+ }
+ data &= 0x7fffffff;
+ /* remapped to SOC DRAM by adding data << 4 */
+ memory_region_set_alias_offset(s->tsp_sdram_remap,
+ (uint64_t) data << 4);
+ break;
+ case AST2700_SCU_TSP_REMAP_SIZE_2:
+ if (s->tsp_sdram_remap == NULL) {
+ return;
+ }
+ data &= 0x3fffffff;
+ memory_region_set_size(s->tsp_sdram_remap, data);
+ break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -989,6 +1009,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_SCU_SSP_REMAP_SIZE_1] = 0x02000000,
[AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
[AST2700_SCU_SSP_REMAP_SIZE_2] = 0x02000000,
+ [AST2700_SCU_TSP_CTRL_1] = 0x42E00000,
+ [AST2700_SCU_TSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 17/21] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (15 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 16/21] hw/misc/aspeed_scu: Add SCU support for TSP " Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 18/21] hw/misc/aspeed_scu: Implement TSP " Jamin Lin via
` (4 subsequent siblings)
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
This patch implements SSP reset and power control logic in the SCU for AST2700.
It introduces support for the following behavior:
1. SSP Reset Trigger (via SCU 0x220):
- SSP reset is triggered by writing 1 to bit 30 (RW1S) of SYS_RESET_CTRL_1.
2. SSP Reset State and Source Hold (via SCU 0x120):
- Upon reset, bit 8 (RST_RB) is set to indicate the SSP is in reset.
- Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an external source.
- Bit 1 (RST) is a software-controlled bit used to request holding SSP in reset.
- If an external reset source is present and bit 1 is set, bit 9 (RST_HOLD_RB)
will also be asserted to indicate the SSP is being held in reset.
- If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.
3. Hold Release and Power-on:
- If RST_HOLD_RB is clear (0), SSP is powered on immediately after reset is deasserted.
- If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to SSP_CTRL_0 to release
the hold and power on SSP explicitly.
- Writing ENABLE (bit 0) is a one-shot operation and will auto-clear after execution.
4. Reset Status Clear (via SCU 0x204):
- The reset status can be cleared by writing 1 to bit 30 (RW1C) of SYS_RST_CLR_1,
which will deassert RST_SRC_RB and potentially trigger power-on if no hold is active.
5. SSP Power Control Logic:
- `handle_ssp_tsp_on()` clears RST_SRC_RB and RST_RB (if not held), and invokes
`arm_set_cpu_on_and_reset(cpuid)` to power on the SSP core (CPUID 4).
- `handle_ssp_tsp_off()` sets RST_RB and RST_SRC_RB; if RST is active, also asserts
RST_HOLD_RB and invokes `arm_set_cpu_off(cpuid)`.
6. Register Initialization and Definitions:
- Adds SCU register definitions for SSP_CTRL_0 (0x120), SYS_RST_CTRL_1 (0x220),
and SYS_RST_CLR_1 (0x204).
- Updates the reset values for these registers during SCU initialization.
The default values are based on EVB (evaluation board) register dump observations.
This patch enables proper modeling of SSP lifecycle management across reset,
hold, and power-on states for the AST2700 SoC.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 94 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 21a0d1ad5c..50f3f6ff17 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -20,6 +20,7 @@
#include "qemu/guest-random.h"
#include "qemu/module.h"
#include "trace.h"
+#include "target/arm/arm-powerctl.h"
#define TO_REG(offset) ((offset) >> 2)
@@ -144,6 +145,7 @@
#define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C)
/* SSP TSP */
+#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)
#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124)
#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128)
#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148)
@@ -152,6 +154,14 @@
#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154)
#define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168)
#define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194)
+#define AST2700_SSP_TSP_ENABLE BIT(0)
+#define AST2700_SSP_TSP_RST BIT(1)
+#define AST2700_SSP_TSP_RST_RB BIT(8)
+#define AST2700_SSP_TSP_RST_HOLD_RB BIT(9)
+#define AST2700_SSP_TSP_RST_SRC_RB BIT(10)
+#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
+#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
+#define AST2700_SCU_SYS_RST_SSP BIT(30)
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
@@ -911,6 +921,35 @@ static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
return s->regs[reg];
}
+static void handle_ssp_tsp_on(struct AspeedSCUState *s, int cpuid)
+{
+ int reg = AST2700_SCU_SSP_CTRL_0;
+ uint32_t val = s->regs[reg];
+
+ val &= ~AST2700_SSP_TSP_RST_SRC_RB;
+ if (!(val & AST2700_SSP_TSP_RST_HOLD_RB)) {
+ val &= ~AST2700_SSP_TSP_RST_RB;
+ arm_set_cpu_on_and_reset(cpuid);
+ }
+
+ s->regs[reg] = val;
+}
+
+static void handle_ssp_tsp_off(struct AspeedSCUState *s, int cpuid)
+{
+ int reg = AST2700_SCU_SSP_CTRL_0;
+ uint32_t val = s->regs[reg];
+
+ val |= AST2700_SSP_TSP_RST_RB;
+ val |= AST2700_SSP_TSP_RST_SRC_RB;
+ if (val & AST2700_SSP_TSP_RST) {
+ val |= AST2700_SSP_TSP_RST_HOLD_RB;
+ }
+ arm_set_cpu_off(cpuid);
+
+ s->regs[reg] = val;
+}
+
static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
uint64_t data64, unsigned size)
{
@@ -919,6 +958,9 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
/* Truncate here so bitwise operations below behave as expected */
uint32_t data = data64;
MemoryRegion *mr;
+ uint32_t active;
+ uint32_t oldval;
+ int cpuid;
if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -930,6 +972,40 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
trace_aspeed_ast2700_scu_write(offset, size, data);
switch (reg) {
+ case AST2700_SCU_SSP_CTRL_0:
+ cpuid = 4;
+ oldval = s->regs[reg];
+ data &= 0xff;
+ active = oldval ^ data;
+
+ /*
+ * If reset bit is being released (1 -> 0) and no other reset source
+ * is active, clear HOLD_RB and power on the corresponding CPU.
+ */
+ if ((active & AST2700_SSP_TSP_RST) && !(data & AST2700_SSP_TSP_RST)) {
+ s->regs[reg] &= ~AST2700_SSP_TSP_RST_HOLD_RB;
+ if ((oldval & AST2700_SSP_TSP_RST_RB) &&
+ !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) {
+ handle_ssp_tsp_on(s, cpuid);
+ }
+ }
+
+ /*
+ * If ENABLE bit is newly set and reset state is ready,
+ * clear HOLD_RB and power on the corresponding CPU.
+ */
+ if ((active & AST2700_SSP_TSP_ENABLE) &&
+ (oldval & AST2700_SSP_TSP_RST_RB) &&
+ (oldval & AST2700_SSP_TSP_RST_HOLD_RB) &&
+ !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) {
+ s->regs[reg] &= ~AST2700_SSP_TSP_RST_HOLD_RB;
+ handle_ssp_tsp_on(s, cpuid);
+ }
+
+ /* Auto-clear the ENABLE bit (one-shot behavior) */
+ data &= ~AST2700_SSP_TSP_ENABLE;
+ s->regs[reg] = (s->regs[reg] & ~0xff) | (data & 0xff);
+ return;
case AST2700_SCU_SSP_CTRL_1:
case AST2700_SCU_SSP_CTRL_2:
mr = (reg == AST2700_SCU_SSP_CTRL_1) ?
@@ -976,6 +1052,22 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
data &= 0x3fffffff;
memory_region_set_size(s->tsp_sdram_remap, data);
break;
+ case AST2700_SCU_SYS_RST_CTRL_1:
+ oldval = s->regs[reg];
+ active = data & ~oldval;
+ if (active & AST2700_SCU_SYS_RST_SSP) {
+ handle_ssp_tsp_off(s, 4);
+ }
+ s->regs[reg] |= active;
+ return;
+ case AST2700_SCU_SYS_RST_CLR_1:
+ oldval = s->regs[AST2700_SCU_SYS_RST_CTRL_1];
+ active = data & oldval;
+ if (active & AST2700_SCU_SYS_RST_SSP) {
+ handle_ssp_tsp_on(s, 4);
+ }
+ s->regs[AST2700_SCU_SYS_RST_CTRL_1] &= ~active;
+ return;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -1003,6 +1095,7 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_HW_STRAP1_SEC1] = 0x000000FF,
[AST2700_HW_STRAP1_SEC2] = 0x00000000,
[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
+ [AST2700_SCU_SSP_CTRL_0] = 0x000007FE,
[AST2700_SCU_SSP_CTRL_1] = 0x40000000,
[AST2700_SCU_SSP_CTRL_2] = 0x42C00000,
[AST2700_SCU_SSP_REMAP_ADDR_1] = 0x02000000,
@@ -1011,6 +1104,7 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_SCU_SSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_TSP_CTRL_1] = 0x42E00000,
[AST2700_SCU_TSP_REMAP_SIZE_2] = 0x02000000,
+ [AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 18/21] hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (16 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 17/21] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support Jamin Lin via
` (3 subsequent siblings)
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
This patch implements TSP reset and power control logic in the SCU module
for AST2700. It introduces support for the following behavior:
1. TSP Reset Trigger (via SCU 0x224):
- TSP reset is triggered by writing 1 to bit 9 (RW1S) of SYS_RESET_CTRL_2.
2. TSP Reset State and Source Hold (via SCU 0x160):
- Upon reset, bit 8 (RST_RB) is set to indicate the TSP is in reset.
- Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an external source.
- Bit 1 (RST) is a software-controlled bit used to request holding TSP in reset.
- If an external reset source is present and bit 1 is set, bit 9 (RST_HOLD_RB)
will also be asserted to indicate the TSP is being held in reset.
- If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.
3. Hold Release and Power-on:
- If RST_HOLD_RB is clear (0), TSP is powered on immediately after reset is deasserted.
- If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to TSP_CTRL_0 to release
the hold and power on TSP explicitly.
- Writing ENABLE (bit 0) is a one-shot operation and will auto-clear after execution.
4. Reset Status Clear (via SCU 0x224):
- The reset status can be cleared by writing 1 to bit 9 (RW1C) of SYS_RST_CLR_2,
which will deassert RST_SRC_RB and potentially trigger power-on if no hold is active.
5. TSP Power Control Logic:
- handle_ssp_tsp_on() clears RST_SRC_RB and RST_RB (if not held), and invokes
arm_set_cpu_on_and_reset(cpuid) to power on the TSP core (CPUID 5).
- handle_ssp_tsp_off() sets RST_RB and RST_SRC_RB; if RST is active, also asserts
RST_HOLD_RB and invokes arm_set_cpu_off(cpuid).
The default values are based on EVB (evaluation board) register dump observations.
TSP reset control shares the same helper functions and register bit layout as SSP,
with logic selected by cpuid and distinct external reset sources.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 31 ++++++++++++++++++++++++++++---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index 50f3f6ff17..ee31a9aabd 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -152,6 +152,7 @@
#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14c)
#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150)
#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154)
+#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)
#define AST2700_SCU_TSP_CTRL_1 TO_REG(0x168)
#define AST2700_SCU_TSP_REMAP_SIZE_2 TO_REG(0x194)
#define AST2700_SSP_TSP_ENABLE BIT(0)
@@ -162,6 +163,9 @@
#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)
#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)
#define AST2700_SCU_SYS_RST_SSP BIT(30)
+#define AST2700_SCU_SYS_RST_CTRL_2 TO_REG(0x220)
+#define AST2700_SCU_SYS_RST_CLR_2 TO_REG(0x224)
+#define AST2700_SCU_SYS_RST_TSP BIT(9)
#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
@@ -923,7 +927,7 @@ static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
static void handle_ssp_tsp_on(struct AspeedSCUState *s, int cpuid)
{
- int reg = AST2700_SCU_SSP_CTRL_0;
+ int reg = (cpuid == 4) ? AST2700_SCU_SSP_CTRL_0 : AST2700_SCU_TSP_CTRL_0;
uint32_t val = s->regs[reg];
val &= ~AST2700_SSP_TSP_RST_SRC_RB;
@@ -937,7 +941,7 @@ static void handle_ssp_tsp_on(struct AspeedSCUState *s, int cpuid)
static void handle_ssp_tsp_off(struct AspeedSCUState *s, int cpuid)
{
- int reg = AST2700_SCU_SSP_CTRL_0;
+ int reg = (cpuid == 4) ? AST2700_SCU_SSP_CTRL_0 : AST2700_SCU_TSP_CTRL_0;
uint32_t val = s->regs[reg];
val |= AST2700_SSP_TSP_RST_RB;
@@ -973,7 +977,8 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
switch (reg) {
case AST2700_SCU_SSP_CTRL_0:
- cpuid = 4;
+ case AST2700_SCU_TSP_CTRL_0:
+ cpuid = (reg == AST2700_SCU_SSP_CTRL_0) ? 4 : 5;
oldval = s->regs[reg];
data &= 0xff;
active = oldval ^ data;
@@ -1068,6 +1073,24 @@ static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
}
s->regs[AST2700_SCU_SYS_RST_CTRL_1] &= ~active;
return;
+ case AST2700_SCU_SYS_RST_CTRL_2:
+ data &= 0x00001fff;
+ oldval = s->regs[reg];
+ active = data & ~oldval;
+ if (data & AST2700_SCU_SYS_RST_TSP) {
+ handle_ssp_tsp_off(s, 5);
+ }
+ s->regs[reg] |= data;
+ return;
+ case AST2700_SCU_SYS_RST_CLR_2:
+ data &= 0x00001fff;
+ oldval = s->regs[AST2700_SCU_SYS_RST_CTRL_2];
+ active = data & oldval;
+ if (active & AST2700_SCU_SYS_RST_TSP) {
+ handle_ssp_tsp_on(s, 5);
+ }
+ s->regs[AST2700_SCU_SYS_RST_CTRL_2] &= ~active;
+ return;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
@@ -1102,9 +1125,11 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
[AST2700_SCU_SSP_REMAP_SIZE_1] = 0x02000000,
[AST2700_SCU_SSP_REMAP_ADDR_2] = 0x00000000,
[AST2700_SCU_SSP_REMAP_SIZE_2] = 0x02000000,
+ [AST2700_SCU_TSP_CTRL_0] = 0x000007FE,
[AST2700_SCU_TSP_CTRL_1] = 0x42E00000,
[AST2700_SCU_TSP_REMAP_SIZE_2] = 0x02000000,
[AST2700_SCU_SYS_RST_CTRL_1] = 0xFFC37FDC,
+ [AST2700_SCU_SYS_RST_CTRL_2] = 0x00001FFF,
[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (17 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 18/21] hw/misc/aspeed_scu: Implement TSP " Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-22 15:21 ` [SPAM] " Cédric Le Goater
2025-07-27 19:51 ` Michael Tokarev
2025-07-17 3:40 ` [PATCH v1 20/21] tests/function/aspeed: Replace manual loader with vbootrom for ast2700fc test Jamin Lin via
` (2 subsequent siblings)
21 siblings, 2 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
The updated boot ROM includes logic to initialize and enable SSP/TSP using SCU
registers, based on reserved-memory regions defined in the device tree.
Its source code is available at:
https://github.com/google/vbootrom/commit/f9eb0bb57decbab860a81712c56132c2102fa98e
Build Information:
Build Date : Jul 17 2025 02:26:07
FW Version : git-f9eb0bb
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
pc-bios/ast27x0_bootrom.bin | Bin 15552 -> 17192 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/pc-bios/ast27x0_bootrom.bin b/pc-bios/ast27x0_bootrom.bin
index 0b9b3a2360e375bb6007ecdf13b39d931870f6fa..339ae7ca8759b9e4e0100bf6e123963bccab4920 100644
GIT binary patch
delta 6044
zcmaJ_3v^V~x&F^N!({RxB=g9`BqV3@BE%$wydSijJmjIFLOS(Y#gf-xB9Vk-5EbeS
zm{nU*>v4|_azP_y-I7__QUOiwZELF7dc}LM#s`9clLQrncBS&l2x0EG&rCvUS9?}Y
z&VRoBzxMywd!HG4Xx~qS{ofIUcJ^Iin`o$EZwO1OKGl<FNTfq1qW8K}D^)X|o?9!`
zu?wV*N@nkf6qoIjEZ&6%@CkH?Fixv0Lt`fINw!?9agk1$PllnpY`A4NdH)g!ScB3g
zuO{(crTV5oo-cr}NtZrK(b4UT)1;3kHy`Y$hR22*cI^3jQX=)j_l5pK8XCTIx7dHB
zS?c$%)Ae7ynf!r(^l~7edpWSc{hgmd50T+%=vB9g<PnHm@7eY)QUQ#UL8tbEK?GfG
z)~OgAx0UIFW34)M55_cXAcURKsk=3WkR_eE6Lf>PQnj@{UcWV>zpF`92G@|Vu2DyJ
zr+(>Rk&cQU6|-VJ+HKnYf=K6nD!Itss8<F@C6m_|cwrdUw|oB3`OL=Xtf1kXS!xdy
z$N%Tn`cGc}eODZu`dBms$Ij1E4_$ubnGwW#Gk9Jzk{S@r=W1Y(N3c;0>3GSYc4It}
z$lP76s4f_`T@Bca5Uo)c3^$4^-%q2yVJ!-G>eW^-UxI?mk1DTR4(t2+busQ-Ka_Gq
zqM>h?^QO|!*BXCTgt{918m-f*CUOtY4+MJCV5|=jNTK+3TSc;O6D>zZPz-JueL^A+
zfBNxsDFPL5!wVnOl-R@6Wl%Wsrl4}BbmZwIa?i(oQk=I+bI$603)lq>vv|LRB1NR)
zJ&2^HV|BR7`KwV=#o)IhYF9ENfmxx$<Xwe|9FZv7M-#3RO`tYXy%~%)czp;VIt=BU
z(E`CkdmyMI&qWA$Xd=kJD_Xq>9uc!eR8Zz7Z#de48@()%_Z>LR@jjv=KIRL_kB9Uo
zB0`tIrwA^sFUDzrdl%=8fD@WS2xUB!AH5#vg+=oynEALimL8=N_{I(hkO>;siuQ>p
zby*mBCcx_^Iyl<F3y?OvL}b_G`l2)&U&0A9nU3svBX#>o`jpc1QR+D&4;LCko~Mnq
z%vL{V$8?#g<8*PhdR$|14~|Ijh@{zTMC3KyJ<;k1%r?vF`YSx(v2_cfP$9H$LrUXH
zidEm5qA^1&X7~(d$SaeFDFNZW>z9#gBA%On9;I$V*bvTa&UaayD7i8jIA}uuHtbQ#
z6{3<bgt>bUsSWzzyDZXL7`Fz)bTL*1;kkOV;`af&@cpX(OLtdeaj3!KP}@Jb`Q3f5
zV<8!m)_feyBVVpe-tDva1QNVFKXowR6R3!XdQ?gbEomn2D4U#>uw<Nca}ZIBcRS1k
zS38r}9`gDB5alWCDa;Y&<825-R<ulpY8{!}!tT-E<g$3RrNur+&49@iWKDZ-nWJ7Y
zdUo<vG=;lDRLuK=N4{696vNXta@PxeRIc%FnS(Kl*ZeKs|C-6Wm&$pP(<GDDkXl~q
zkmVm>5;w9Rau6xMUBh|GZ_-l!7?f*5Ncl31{T>t5jC+E{FR`=wjGU1C-Z^S1cus&v
zlWC990`@Ds^Tk|1GHvm!A}mdaXFm$NT}WoX4ok%Ucfy_u<B3Aj*c!v!C`BTBx1Lla
zs-8VzNEc-GTZ3uokcsRmPYWCRqRHN;bJxFuzG@Jaa!&-s{sweD3adLJC{`=D>-m^4
zM61%0$mmL^4a=?t?A1CQiwwU<c#^e+FBbY)e|U<pk^OhLOAy%dhy`<&L(e4q)uAYR
z28`^n2;1DP(nP6{L#l23$Ipxuk{<;+cvPBrwQrWYzJ$FMQRLE7?3G6pc12I`2lTYi
zcQIh^yKhrj8kAjyvQ(L3M>mt!pLKA;SE~4F$hLhHW4u^D$I}BHR`Blt&4Y!WKga`?
znxy#m5MMVGznnyVLQHrO%XnS~FW((qlbc`dpV}6A>1olwW>kG)v-&l<-K6^9xvY@t
zE9FYCi=6;g3Cs;_aR_TSs~2hnm2as?;rNy77A#CO9{*^Z>Z<|o5TZbW%D3G(w5dOh
z{5N4+9rrDrQfh|L@P1yi8%4#>`z1kJDk)n*PxE*AZi{*mJ%T>=qxStN1{(Yr+3v0;
z^|Ltoo9%kQ?oU(vGh29a^E=b+JF2bgX0HSX^3lG1G_|Zo#cB0+7Gc3Q>ldSx`93UN
zd}C<FoeE=VFvgwu5DtumLM^5D3`=+J`MQae!Bm}6qN9EFEj}7-IZcCaN$z?F(V#1z
z2AkZHnh}p?GGODmR{KFS&5F!erVKW_IFY3c+RBu{7fFb0#9gIW2CCfVfw9G=0=(Z=
zHDn&BA@hJhJ@r+Jd7xG?4k&Kp0P<;6hCq{PpaD5m+$N4`Io6s6&Ixc%hI6E&0vXQC
z9G7x>hTEsS9~I!e;;wHQg7=4M@G!h@;R5j12G1LdXs`hhfC6Jf6zCY-FxC+N_eupQ
z{bxp5XJq;<+%q2kH6)!I!H!c+(h-TI?Sh608pf+My|uY4JrF3;wWgId>qy&1U9Gk<
z8|cdi&PKi_2oD~3adxDT&NbT5s8d?2pp|P7LXy0X4xETC(@B3M>44R=N;L5Go3HV#
z(~=~lvL`Kf3ke6#TISstIS?PeUr6u07U*@OolG!_#q1!L+r=@F2B&qLzo}<>4ce4Y
zB^+gg3HJ)O9k3<V2#M|BR&aDd_6~82yu7CtELYNG(!r~N-qYAy$FP0z!yPINyNfyK
z-Hy5AQCAXg)HCxWcP7>UD+xJeu2^Pei&OGM*~&Unp5#-_)~2eH?_B8P8^Z!+aIt|F
zVwtdaV@?QYY$N7#AyV;AZhmvRSx9snud-G1Ewcsh1*{BMyZ77fw6fRa4565vlouE-
znS!n{vn@Ys8{FbYA2&^uzAn;+9H{r8Sh)X~kmdvLOV)17671|*+r2^so3tg0!gZFA
zS|Ds=D^e?kZv0PVds9<%`)ymS?9ZviF)v>aSh*!s-ms=1DlJP`rtz&zD@y$O8>9m^
zQ^IIN9c(JF8R~!btF&_A2{w|p_?Ajaj7*`#bv7I^M-Y)wY}EXexMDKUi&Kc#hn;TZ
zo4~<cB1OI+#jpDcH6(6P*yb>b?R%qWy9dvw+5PF(RT2Jx{RKU3@Ev_20jKcW;8y+X
z?-Z52i7L}H|1zlg1H=Pi%RT}etNcQ&tag`?7FG*rAmg@#*MOsejE7ikf`xsR9w+oN
zA;T0Cj8`yc+H})1+J&7=&G@rW#eSHXnAjLnY{J1QSW%|zsfzk}=3K$ZUd~Lk9P<Zy
z`z8ZL+$CO5{N%Efoy;s0Oe}VuRVZTf=iMw!vLDP_DipBY^KQ002Z;upVVbZV@xuWc
zvi?u(<h&FecZsbO&CHw?U-b$ic5$&XIE2#SWnmdA+HMA`OSGID!yI|4c)q#slba7u
zm(z=)=?HI`->?l?)^L8n{Sc8DXKI$!bxD%EV}-%ZL*@E!R|e5EnttxenTbFz_SM)2
zkcptJxN~X9HE3g~sir~zn{Q3q{A0-G&oDKD{DW`E+j&+~q_}hVcCe?Ab=`|ZsVE8l
z(O~i_V00sDd`rE6^`C!CayP$3AEXJ*Y~%cY6YgUFGykrP{nh)eYB8@Kw3C~kq9MKt
zyD-|Mp0|=u60+G#DamsP-6LdQGLiq1BzhOIt=T5!M<`le93)JXj>7g-mX1RKK3o^B
zLm=JP1I1eNhPrHKZyxYvFA)n1Dhf&}@=NK~jqUQnQn?_%pqQ#Rwzap&wT(`PTp?$4
z<1d2lZFA<XEq65KH#M;z=BDUZ)W{EHw6KSB6X(yT9C^LtL8rWAxn1sdG<G$&%8H!-
zU`G3c5%j$d`GLmvwibEGiW=t4Ep*+Xz17;Q<+U9f*SE-x&LC@!+}zRG=4g?f9aFMP
zYVB)QR4rXzGtDG7ZFI_Q>w_A(j#fuwi=%6XnH!3m9L`M+$NHc$xe=zgOIYyRa(jfx
z?(WXDo5;!kv-5eMx)yXfx*c5)I9hV=cii96_0R$^gh={_F^K*1v968XPN-Si)^-1;
z#x6&0<3GxGbUGc5+~$rh$JChXhT*o(=3H*PyA{$@)3|<phf`kL2LIQ0v^aP^+Sbd?
zR)^f;c%ZG>Av?Pqj=Tu!a@@;<jfdRX)zRtbay}G_FxYtp@1C0BJzPgqW4EIs6dSp_
zE#l#+w+Qy91?A7=&lQfa<orU{yMchBC!(6%s^}qMcl`6#S{CQA-14mX7p7k0j@aj7
zcFy_tXvru<oI3gGvExTS`RL;hK8&WS+$wx%5yjx<C-{cpKp>q1xHz^CcPFq~4&cJ!
znSO`657=rBKtZ&;TgTqZPZ!@FW|#9TTqiyX1akOT=vstlEm~z9_#!+tnLc5+`FT?{
zGkRj{d!u*EUiNIvFXmJ~7j+l>JNEb9aX;{T2c7>o5ZD#c$*~>4oJRuzc?R~9fMcE;
zpnV271jeCnF@6Z_U0^dOdj{AEVEBU3E^g!+u$WJ7Oo(GKB2gBwtRR~fDEuTri-5^g
z7DPE?8Ng-VV#Mbotp>I-B%F_D1F#*Ru&);8>G@AhQO8(vL9%NAWYV$FRCt_Yc8kvo
z-$Q_cdE*vNfTs>TJjVRu*f=mJu&JDJOeYcT1vYcK@xTs#3(Em^7+4VzzR_@TVSH%O
zX@E25YX>#~EK1`dlJRT>Hhzrh3zHM@a}K$&!i9pN4fg@tdz^i@Fj;>XWZ!YtRG6tB
z2f6=K_EceVwpm9MkI%v~#9S+6ZNj`FqNy5%%59W^C+8&l21-_gTp1+YAe|>!a#3>j
zUXX@Up@@X4^Lc6cbkw+#x4|QyVrz?%_2)s_PqD{~^7Qg7WZ@M1Ls4cz9mo%%WajJ|
zfW3Q)U58K)NZn^FwK#L(evq}F1p)@B<rk0FVPIu5Fy0KG0LuZ^$^KSsVNVqs^#-(S
z`)BMwit`c{fo$;IFqaR3mB8-wvA-7Q<@SKwh2fQe5tr&<AuOGa3uoU4p0~j>z~0B1
zu%X1PKLMm}ggsnRqK^+lvPRgeC7JqKkny8zv?N>a1er6+jHTK7y&#oQR$W>Vej4N%
zd~(*Y-<BrLuFfT%^%zXgFvfmenyFs|GG~k(hg3Vrm18WTEH&H%au>dohS-lw64>o!
z7X7<G(oeJd%Chy>KrTDYc9!Mo^TWY+n*DECUS12x@zbGM@kHhC);~Y1n(68=u@8bJ
zo(0=afG_@YmR+8y9{}n6oZV4gpdSZW_XT^ZJXIebf#`8EIf9p)f>-Ak>{NM)ehbKb
z+Q{r$jO@kh@374~*)0|6!founiUj?6U}wH$k5?3Ar(-4Dawb%>)0J~;u-zce!@LYU
zPoH65ROIQmfPCo;OQ<Z-4}i=$%kHSm)}I0S)3fX+m3iSwsGf`X%G|<i`Q{`(tB-Ch
zxo9w|1B3Dv&)Hup6WMbmF%jHE5742nSn8s@yaAB4=a37)+N!CAs0JYlMF=ntkq>;W
Q=h!2QQpE{_x+?kq0rxu(?EnA(
delta 4461
zcmaJ_3v^TE9sj<2!|jtto0RmKq-`iAeL&l^P2XwDu+9es;*kN4BB&s!RLaIyT;dK#
znds#DMO&FbWVq3+I$X=7=O9+52Pe3dH-m~vDT)QRYJs*&x%+)LX#w5YJ*4-a-}n3e
z@9z<IJwrQxvAc}YdssRBwcsgb2k5NI6XS@xQy_b^gmkUhks<5wc7L29pC2G{kErwd
z#mN?*7~{<d0gsYB1mmPTBRHn@u4H!#)lM2}pJoc}Tu_OR$wj<hDT+QYTkBP4)Mm<a
zC~<!dydqURG1A!4Lh7D9TGzben-P)71M_Ih)rCUK;8L+=c%`Q0y9_d%1U@05n=xOW
zED$$^<z#b~tm@lnmCG<L0IPCaow7Q(*BThSXq5{vsA9JK0Jc0|&QTS@eV0|vhMYn=
zk2*-LJRk~QA3k=Gxa|VTe^9b_s76}zWxuHPRw1Yq@bxe@__IP_dhoU0R;0u)5{q4M
z4i%^q+=X&1h?#`w9;~v<i;3=1@`&Q7B(+CUiRY-wSyv!W9Cc)aRn`*M(R&r8=}TmW
zD~*AXJ>L|{(>26>1<KtdsQYrU%sB%1eo=>-XubENc7D|6no}g+7^H{~cnGob!R(-d
z{-EL~VB{)z_R%7S+7QWP?`6W%jI6+!SSZf`57Fp)z~$rWSc6UO0q=Yp#hid~HTB&#
z`4x${=L~`DBBZ_N346z4Lh4%yai|mf14h1p6FQ<jwBta^rZJ_ZMe-+5%IBO9bXvez
zdy#yQO_S16y2#98d7nygb@;_tWL@Wd0CB3Sj~B~(SiPiomIv$LqBqL`O#xPEnf%95
z84>Cc;paD$rU*pHvlNfW7Yr2233xYtW|Kce4<Jhx&btbIgCj~iueWMZS1v=TdthE=
zix1e<g;i+S>RIU6ndn&i@JQpqUGJg0JH^E(19gf~>*Pl%{9?TK8nUz<wf9kC<*Dou
z6OiHn$HpEDiJ#R)93^U1*22!{kT>YlDI{?e>q87^53fgqq<^nc53^4~;+&JcYX9#n
zk=Mbb5k(n{c5mUyP8GF>#)^Ps-v?ViC;~D+Tg7?i<J8RekG3r`UxTq@@JF@LULyO@
zDL=)yhm!neO4@zw-O#wqVE24bA{T<+4ZfPk=S$TX-^KUEX7L2YB2U&aAuN^ZSX$WZ
zq<H)A>(HT1B+*U_sb7L-@=(`Y6R9})bUb@0?6)Dj1V}xb8lE(%P9%;s5|NSdxpjiQ
zh}DLh7m^XhYCKHqJI4{nMi7i{Qt#2?y_wc~CP1IYHTP|FI-lSUCsA)fo`IfN6CO}h
z4SRfybdos~epHxAefo99QAI@d&+rH6^DHZ(g6?9EMHp!Vdm+L}BiZ=K=@V<9X9RI+
z&`%pqm$SPflarQ+LxnVx$jSXrz2wg$!|1J!cf_H;dd9it=Cj{KTAjbLGtZ+xw+%|<
z$P_40B$D&AqB!1wq7)N}>S-kEs#*mHe1-O5(wV&JJjQqv@*UMJktjXpy$YEplpuLL
zsVTAc;T?qU+4f;mEEy)q5bsSB-Zz3=-lwc}V&Z*)ZFzr-2teJEBgpUoI?G9fOLeG#
zY57u{9o4N9#7)S;AqpkfCf$4$4MgzfKQPw(b&sanmTHLnb=&w!?@-#%_F+^6oiS=5
z8Tq``!nbh!e`#sE5^d9nONi7qT|Y<A@a4wr2|Css7fFrmjktwW-$vu7-W+MOCweG#
zGk=mc^404~lS?2SW3zOIhOxGJ(NIZ`vm=H_XiZy@v6?2V0GkK57n>uW!8e-G9&0j<
zB)<Kf($tF<KaZ`U2LbbCILc$Yllvn%nFE6f_F>kVvO010|C?b;O%kjX?EchjA+drz
zoBBd%K$+IU63z3AI>}I>Z@Rt17)o;BmE)LNL)Y9un*TPIW}+ccb%=2owIqTodWh9$
zXeV9~sh1ZHOLKFwqk<hYPoa72EA#YF)k!TJG*6k4?t+8-fN{atdjhG?gdsO^MF+#O
zsNwTy)=x>NbJ-hH9-%fiJ}p5|Mwlfnmp;WFNGqX_<8K0MPcv#ZC$Fnur_%B#{pp6H
z=abQGN3U{giBr>QwaTlTYEA9`R%wEJs$F9Usb2-V^TzCIxn1_>sYUcK`*Lc<J&hub
zFp`9oO9bNRQBNN&w$#bqJ4cizzGvb5^`blX;0(7MM;aCpUBq@Vc4Z&mGY(icHHMHV
zH$GMC?d)0hSh{|WcSvz;mq@+u)b@DXAMU~dJomkit+r0g#%XWq`8`#4vrmv8?&sfu
zJFy^f1UQ`0B<KBWienyiMYjWA1Hb>ma#CVgU;1P!GdfK>X|$4K`7=*jg`SkB9i%1f
zCzgbSg+awy951(#v7fzYNy0|*rX?Y!YglRWU=!mm@owbnw32;l$)n?0REC~rvuPO_
zbdcSbaR;5owq|6+Y{rZ_oGcGwH{mxnzCb(Kry0iEn=>@i9NCKO5w!Z13VR2;J2RFw
zXGO;7z;_BUmv-Dx9Ip%7LwreMgUi&1T|=nH5po|w)iO_}#(7N?z320&%<pT@L79mw
zn{8KD8@vrP&(i9ak;V_lx|R1NFWspjTtsHOI<QAZtrcQ6joMv`1VfJg53G&acOfR;
z<?9ZZHVG)9QH;4%Ly5&<B>I)FV*)?NxT97OP1hAG-wFqCQ@9*-xtlKuHa}|;UBFgk
z-B0JR_p=rhY_4jpkTc<TCt8QEwC}GhKQO+|@5I)`k4~R{d;B1aGR7IH<*JqpU&VDX
z2PS=VsPNVb&0|kz>#e8xEDgz72?t#_lzcd-W`wVXk;YrrFS+@&b!N{J@^XrE^NMq9
zq;mC>rraV^?u^`gQnhx)s%55`OBx<B6`Q84!M||w$cl!nWd#rA<=F~YQI4@~S?*fO
zF65nIALZMal5e0#n4uugc~nu>;UprJS(Ou3Z=JAhd<~0qN4y;VN?229bI7aGmT|w+
z2p!?)K0W)dGpA0UIC<>&1kT0fNPQ;ZFTX`KpHvic03saQ#XrDi1~D9*1lKfj8rUL^
zaeJn%8rD@{7RV`ft)SScJEJJL7mqz$&rEDl>A**I^Y?sUHemBPGpJ{qSj~jH;pVY`
zdwi}7yyds(<QTv4yMU$hxp+9X3z++iQlgkRf`^0q0D8Vh>;l#ftX5?aG6U~kVEt#<
z!?tWG7Wds{XW15;K`MpVaF*@28JyUC$<DKiQW~7Zl{Wx83~V$z9NP%&I<Q+KeGOP7
z?nK<sZIS*c7${&q_XF^B;8{5j564aevvw;}ZwvJ@z#0%ERT?2C{uXigceBTf4Dn`&
zT^P3AGHe5OrJMbs$RI6(*x$`QE=rSdVIt%ly9Trs;_`DWzStmjL0tbCD~E`4gLndB
ztOg!_#-0IM3UR)Vc_G$8T<v53fVctTP9OWGI9u8a@uH8Vm88Y@LNxnt_jL$ZqMton
zVvrKY@wLsKD@n_)f#?P^H0U-De-W^aw_v=nRs&n_XXi>Rk_X~GKbugRopc=H?w*@=
zc(N}7+XZYL^OwZ1$4e(mi4q}~d)RZO2FVUF_B?y5G&`&T;%m5PU1VF!<C#(#C+!AO
z)5{EHX;L@D<-P33Wfmzi1eSZ*FCmsf+}z8&WyR8Zh_(x?uPiNW7sUA&&|2)PvcyT%
zS%mw0oX-O2V98}MY(aUnq(O+D3+&1A6e$zp<qK>}d2ZM;hz+>q1$cenxq&o)&V-8W
zu#Y$ogB#h~rFvFdq07Dw#Ezd^W9w(eR%zR~DyF&X=K4v8d2<+2_62*XB2B7=c=!vp
zzam%K2yy2{X0RK=%^>Z@*S-8}igcQjF0xtn0!bH+p)Wa!dF-07Qhe3nr|Aavrrm75
zhwmocKiE!q^KJmKwog$GtNEN*86)ij(%Z)@l?KTNaj1{oTbUiE<3G+WDat;Tx4kk>
zss-Y{#P(NOBp1Z~OYGm^wL@Hljo!tQ3v{+SVEDw%4U8M?1)&v$PRQyCtKAyDEv%Y_
zx<g);UKv;2q-hpwSbdc?ED>wQivP6O%f7DEvz=ACoLV4zfjCCzs(Gwtnws15xDLEt
S@EX)+x=|G_%m|U^82$?nlNqA`
--
2.43.0
^ permalink raw reply [flat|nested] 61+ messages in thread* Re: [SPAM] [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-17 3:40 ` [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support Jamin Lin via
@ 2025-07-22 15:21 ` Cédric Le Goater
2025-07-23 2:42 ` Jamin Lin
2025-07-27 19:51 ` Michael Tokarev
1 sibling, 1 reply; 61+ messages in thread
From: Cédric Le Goater @ 2025-07-22 15:21 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee
Hello Jamin,
On 7/17/25 05:40, Jamin Lin wrote:
> The updated boot ROM includes logic to initialize and enable SSP/TSP using SCU
> registers, based on reserved-memory regions defined in the device tree.
>
> Its source code is available at:
> https://github.com/google/vbootrom/commit/f9eb0bb57decbab860a81712c56132c2102fa98e
>
> Build Information:
> Build Date : Jul 17 2025 02:26:07
> FW Version : git-f9eb0bb
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> pc-bios/ast27x0_bootrom.bin | Bin 15552 -> 17192 bytes
> 1 file changed, 0 insertions(+), 0 deletions(-)
This patch is not applying for some reason I don't know.
Could you give it a try please ?
Thanks,
C.
^ permalink raw reply [flat|nested] 61+ messages in thread
* RE: [SPAM] [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-22 15:21 ` [SPAM] " Cédric Le Goater
@ 2025-07-23 2:42 ` Jamin Lin
0 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin @ 2025-07-23 2:42 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
Hi Cédric
> Subject: Re: [SPAM] [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with
> SSP/TSP SCU initialization support
>
> Hello Jamin,
>
> On 7/17/25 05:40, Jamin Lin wrote:
> > The updated boot ROM includes logic to initialize and enable SSP/TSP
> > using SCU registers, based on reserved-memory regions defined in the device
> tree.
> >
> > Its source code is available at:
> >
> https://github.com/google/vbootrom/commit/f9eb0bb57decbab860a81712c56
> 1
> > 32c2102fa98e
> >
> > Build Information:
> > Build Date : Jul 17 2025 02:26:07
> > FW Version : git-f9eb0bb
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> > pc-bios/ast27x0_bootrom.bin | Bin 15552 -> 17192 bytes
> > 1 file changed, 0 insertions(+), 0 deletions(-)
> This patch is not applying for some reason I don't know.
>
> Could you give it a try please ?
>
It seems work to me. My git version: git version 2.43.0(Ubuntu 24.04)
1. git clone https://github.com/qemu/qemu.git
2. Download patch series by clicked series button at the right-top side, https://patchwork.kernel.org/project/qemu-devel/cover/20250717034054.1903991-1-jamin_lin@aspeedtech.com/
3. cd qemu
4. git log
commit 9e601684dc24a521bb1d23215a63e5c6e79ea0bb (tag: v10.1.0-rc0, origin/staging, origin/master, origin/HEAD)
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: Tue Jul 22 15:48:48 2025 -0400
Update version for the v10.1.0-rc0 release
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
5. git am ../Control-coprocessor-reset-for-AST2700.patch
Applying: hw/arm/aspeed_ast27x0-fc: Support VBootRom
Applying: hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve
Applying: hw/arm/ast27x0: Move TSP coprocessor initialization from machine to SoC leve
Applying: hw/arm/aspeed_ast27x0-ssp: Switch SSP memory to SDRAM and use dram_container for remap support
Applying: hw/arm/aspeed_ast27x0-tsp: Switch TSP memory to SDRAM and use dram_container for remap support
Applying: hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device realization order
Applying: hw/arm/ast27x0: Add SRAM alias for TSP and ensure correct device realization order
Applying: hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device realization order
Applying: hw/arm/ast27x0: Add SCU alias for TSP and ensure correct device realization order
Applying: hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing
Applying: hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap and update realization order
Applying: hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap and update realization order
Applying: hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior
Applying: hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior
Applying: hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
Applying: hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
Applying: hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers
Applying: hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers
Applying: pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
Applying: tests/function/aspeed: Replace manual loader with vbootrom for ast2700fc test
Applying: docs: Add support vbootrom for ast2700fc
6. Download this patch by clicked mbox button at the right-top side, https://patchwork.kernel.org/project/qemu-devel/patch/20250717034054.1903991-20-jamin_lin@aspeedtech.com/
7. git am ../v1-19-21-pc-bios-Update-AST27x0-vBootrom-with-SSP-TSP-SCU-initialization-support.patch
Applying: pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
8. git log
commit b4b9da1683e178a1f99a0e2b11beda0aade8b0dc (HEAD -> master)
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date: Thu Jul 17 11:40:47 2025 +0800
pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
The updated boot ROM includes logic to initialize and enable SSP/TSP using SCU
registers, based on reserved-memory regions defined in the device tree.
Its source code is available at:
https://github.com/google/vbootrom/commit/f9eb0bb57decbab860a81712c56132c2102fa98e
Build Information:
Build Date : Jul 17 2025 02:26:07
FW Version : git-f9eb0bb
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
commit 9e601684dc24a521bb1d23215a63e5c6e79ea0bb (tag: v10.1.0-rc0, origin/staging, origin/master, origin/HEAD)
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: Tue Jul 22 15:48:48 2025 -0400
Update version for the v10.1.0-rc0 release
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Thanks-Jamin
> Thanks,
>
> C.
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-17 3:40 ` [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support Jamin Lin via
2025-07-22 15:21 ` [SPAM] " Cédric Le Goater
@ 2025-07-27 19:51 ` Michael Tokarev
2025-07-28 6:49 ` Cédric Le Goater
1 sibling, 1 reply; 61+ messages in thread
From: Michael Tokarev @ 2025-07-27 19:51 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Hao Wu, Havard Skinnemoen
On 17.07.2025 06:40, Jamin Lin via wrote:
> The updated boot ROM includes logic to initialize and enable SSP/TSP using SCU
> registers, based on reserved-memory regions defined in the device tree.
>
> Its source code is available at:
> https://github.com/google/vbootrom/commit/f9eb0bb57decbab860a81712c56132c2102fa98e
How to (re)build this one?
Please add build instructions to roms/Makefile. I dunno how this one is
related to roms/vbootrom which is already used for npcmxxx_bootrom.bin
files - maybe all the 3 bootroms should be kept in sync.
Right now, with no instructions in roms/Makefile, it's problematic.
Thanks,
/mjt
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-27 19:51 ` Michael Tokarev
@ 2025-07-28 6:49 ` Cédric Le Goater
2025-07-28 7:02 ` Jamin Lin via
2025-07-28 8:32 ` Michael Tokarev
0 siblings, 2 replies; 61+ messages in thread
From: Cédric Le Goater @ 2025-07-28 6:49 UTC (permalink / raw)
To: Michael Tokarev, Jamin Lin, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Hao Wu, Havard Skinnemoen
On 7/27/25 21:51, Michael Tokarev wrote:
> On 17.07.2025 06:40, Jamin Lin via wrote:
>> The updated boot ROM includes logic to initialize and enable SSP/TSP using SCU
>> registers, based on reserved-memory regions defined in the device tree.
>>
>> Its source code is available at:
>> https://github.com/google/vbootrom/commit/f9eb0bb57decbab860a81712c56132c2102fa98e
>
> How to (re)build this one?
This should be the same as npcm*xx_bootrom.
> Please add build instructions to roms/Makefile. I dunno how this one is
> related to roms/vbootrom which is already used for npcmxxx_bootrom.bin
> files - maybe all the 3 bootroms should be kept in sync.
I think they are relatively independent. Each has its own directory.
> Right now, with no instructions in roms/Makefile, it's problematic.
Oh I missed that. My bad.
Jamin,
Can you please send an update asap ?
Thanks,
C.
^ permalink raw reply [flat|nested] 61+ messages in thread
* RE: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-28 6:49 ` Cédric Le Goater
@ 2025-07-28 7:02 ` Jamin Lin via
2025-07-28 7:11 ` Cédric Le Goater
2025-07-28 7:11 ` Michael Tokarev
2025-07-28 8:32 ` Michael Tokarev
1 sibling, 2 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-28 7:02 UTC (permalink / raw)
To: Cédric Le Goater, Michael Tokarev, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Hao Wu, Havard Skinnemoen
Hi Cédric,
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Monday, July 28, 2025 2:50 PM
> To: Michael Tokarev <mjt@tls.msk.ru>; Jamin Lin
> <jamin_lin@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>;
> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>;
> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley
> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
> list:All patches CC here <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Hao Wu <wuhaotsh@google.com>;
> Havard Skinnemoen <hskinnemoen@google.com>
> Subject: Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP
> SCU initialization support
>
> On 7/27/25 21:51, Michael Tokarev wrote:
> > On 17.07.2025 06:40, Jamin Lin via wrote:
> >> The updated boot ROM includes logic to initialize and enable SSP/TSP
> >> using SCU registers, based on reserved-memory regions defined in the
> device tree.
> >>
> >> Its source code is available at:
> >>
> https://github.com/google/vbootrom/commit/f9eb0bb57decbab860a81712c56
> >> 132c2102fa98e
> >
> > How to (re)build this one?
>
> This should be the same as npcm*xx_bootrom.
>
> > Please add build instructions to roms/Makefile. I dunno how this one
> > is related to roms/vbootrom which is already used for
> > npcmxxx_bootrom.bin files - maybe all the 3 bootroms should be kept in
> sync.
>
> I think they are relatively independent. Each has its own directory.
>
> > Right now, with no instructions in roms/Makefile, it's problematic.
>
> Oh I missed that. My bad.
>
> Jamin,
>
> Can you please send an update asap ?
>
It seems this patch fix this issue, https://patchwork.kernel.org/project/qemu-devel/patch/607a943a587248fbe0ff0897de80aee98a093caa.1753654515.git.mjt@tls.msk.ru/
Do I need to update vbootrom/ast27x0/Makefile?
I set "?=" to make user able to set variables in the command line.
1.
export CC=aarch64-linux-gnu-gcc
make
2. make CC=aarch64-linux-gnu-gcc
3. Update Make file and user only need to issue "make"
diff --git a/ast27x0/Makefile b/ast27x0/Makefile
index 5d13ba1..45c069a 100644
--- a/ast27x0/Makefile
+++ b/ast27x0/Makefile
@@ -13,11 +13,11 @@
# See the License for the specific language governing permissions and
# limitations under the License.
-CROSS_COMPILE ?= aarch64-linux-gnu-
+CROSS_COMPILE = aarch64-linux-gnu-
-CC ?= $(CROSS_COMPILE)gcc
-OBJCOPY ?= $(CROSS_COMPILE)objcopy
-OBJDUMP ?= $(CROSS_COMPILE)objdump
+CC = $(CROSS_COMPILE)gcc
+OBJCOPY = $(CROSS_COMPILE)objcopy
+OBJDUMP = $(CROSS_COMPILE)objdump
> Thanks,
>
> C.
>
^ permalink raw reply related [flat|nested] 61+ messages in thread
* Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-28 7:02 ` Jamin Lin via
@ 2025-07-28 7:11 ` Cédric Le Goater
2025-07-28 7:11 ` Michael Tokarev
1 sibling, 0 replies; 61+ messages in thread
From: Cédric Le Goater @ 2025-07-28 7:11 UTC (permalink / raw)
To: Jamin Lin, Michael Tokarev, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Hao Wu, Havard Skinnemoen
On 7/28/25 09:02, Jamin Lin wrote:
> Hi Cédric,
>
>> From: Cédric Le Goater <clg@kaod.org>
>> Sent: Monday, July 28, 2025 2:50 PM
>> To: Michael Tokarev <mjt@tls.msk.ru>; Jamin Lin
>> <jamin_lin@aspeedtech.com>; Peter Maydell <peter.maydell@linaro.org>;
>> Steven Lee <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>;
>> Andrew Jeffery <andrew@codeconstruct.com.au>; Joel Stanley
>> <joel@jms.id.au>; open list:ASPEED BMCs <qemu-arm@nongnu.org>; open
>> list:All patches CC here <qemu-devel@nongnu.org>
>> Cc: Troy Lee <troy_lee@aspeedtech.com>; Hao Wu <wuhaotsh@google.com>;
>> Havard Skinnemoen <hskinnemoen@google.com>
>> Subject: Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP
>> SCU initialization support
>>
>> On 7/27/25 21:51, Michael Tokarev wrote:
>>> On 17.07.2025 06:40, Jamin Lin via wrote:
>>>> The updated boot ROM includes logic to initialize and enable SSP/TSP
>>>> using SCU registers, based on reserved-memory regions defined in the
>> device tree.
>>>>
>>>> Its source code is available at:
>>>>
>> https://github.com/google/vbootrom/commit/f9eb0bb57decbab860a81712c56
>>>> 132c2102fa98e
>>>
>>> How to (re)build this one?
>>
>> This should be the same as npcm*xx_bootrom.
>>
>>> Please add build instructions to roms/Makefile. I dunno how this one
>>> is related to roms/vbootrom which is already used for
>>> npcmxxx_bootrom.bin files - maybe all the 3 bootroms should be kept in
>> sync.
>>
>> I think they are relatively independent. Each has its own directory.
>>
>>> Right now, with no instructions in roms/Makefile, it's problematic.
>>
>> Oh I missed that. My bad.
>>
>> Jamin,
>>
>> Can you please send an update asap ?
>>
>
> It seems this patch fix this issue, https://patchwork.kernel.org/project/qemu-devel/patch/607a943a587248fbe0ff0897de80aee98a093caa.1753654515.git.mjt@tls.msk.ru/
> Do I need to update vbootrom/ast27x0/Makefile?
> I set "?=" to make user able to set variables in the command line.
>
> 1.
> export CC=aarch64-linux-gnu-gcc
> make
> 2. make CC=aarch64-linux-gnu-gcc
>
> 3. Update Make file and user only need to issue "make"
> diff --git a/ast27x0/Makefile b/ast27x0/Makefile
> index 5d13ba1..45c069a 100644
> --- a/ast27x0/Makefile
> +++ b/ast27x0/Makefile
> @@ -13,11 +13,11 @@
> # See the License for the specific language governing permissions and
> # limitations under the License.
>
> -CROSS_COMPILE ?= aarch64-linux-gnu-
> +CROSS_COMPILE = aarch64-linux-gnu-
>
> -CC ?= $(CROSS_COMPILE)gcc
> -OBJCOPY ?= $(CROSS_COMPILE)objcopy
> -OBJDUMP ?= $(CROSS_COMPILE)objdump
> +CC = $(CROSS_COMPILE)gcc
> +OBJCOPY = $(CROSS_COMPILE)objcopy
> +OBJDUMP = $(CROSS_COMPILE)objdump
>
It would be nice to fix vbootrom and avoid the workaround in QEMU.
Thanks,
C.
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-28 7:02 ` Jamin Lin via
2025-07-28 7:11 ` Cédric Le Goater
@ 2025-07-28 7:11 ` Michael Tokarev
2025-07-28 7:41 ` Jamin Lin via
1 sibling, 1 reply; 61+ messages in thread
From: Michael Tokarev @ 2025-07-28 7:11 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Hao Wu, Havard Skinnemoen
On 28.07.2025 10:02, Jamin Lin wrote:
> It seems this patch fix this issue, https://patchwork.kernel.org/project/qemu-devel/patch/607a943a587248fbe0ff0897de80aee98a093caa.1753654515.git.mjt@tls.msk.ru/
Yeah, I posted that patch yesterday after realizing our
roms/vbootrom submodule is outdated.
> Do I need to update vbootrom/ast27x0/Makefile?
> I set "?=" to make user able to set variables in the command line.
The prob with `CC ?=` construct is that CC variable is always
set by make, so this line becomes useless. The question mark
should be removed, that's all.
> 1.
> export CC=aarch64-linux-gnu-gcc
> make
> 2. make CC=aarch64-linux-gnu-gcc
>
> 3. Update Make file and user only need to issue "make"
See how it's done in other subdirs of vbootrom. You only need
to remove ? from CC variable assignment.
Distinction between 1 and 2 is `make -e` command-line switch.
Thanks
/mjt
^ permalink raw reply [flat|nested] 61+ messages in thread
* RE: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-28 7:11 ` Michael Tokarev
@ 2025-07-28 7:41 ` Jamin Lin via
2025-07-29 9:12 ` Cédric Le Goater
0 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin via @ 2025-07-28 7:41 UTC (permalink / raw)
To: Michael Tokarev, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Hao Wu, Havard Skinnemoen
Hi Michael, Cédric
> From: Michael Tokarev <mjt@tls.msk.ru>
> Sent: Monday, July 28, 2025 3:12 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
> Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Hao Wu <wuhaotsh@google.com>;
> Havard Skinnemoen <hskinnemoen@google.com>
> Subject: Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP
> SCU initialization support
>
> On 28.07.2025 10:02, Jamin Lin wrote:
>
> > It seems this patch fix this issue,
> > https://patchwork.kernel.org/project/qemu-devel/patch/607a943a587248fb
> > e0ff0897de80aee98a093caa.1753654515.git.mjt@tls.msk.ru/
>
> Yeah, I posted that patch yesterday after realizing our roms/vbootrom
> submodule is outdated.
>
> > Do I need to update vbootrom/ast27x0/Makefile?
> > I set "?=" to make user able to set variables in the command line.
>
> The prob with `CC ?=` construct is that CC variable is always set by make, so
> this line becomes useless. The question mark should be removed, that's all.
>
> > 1.
> > export CC=aarch64-linux-gnu-gcc
> > make
> > 2. make CC=aarch64-linux-gnu-gcc
> >
> > 3. Update Make file and user only need to issue "make"
>
> See how it's done in other subdirs of vbootrom. You only need to remove ?
> from CC variable assignment.
>
> Distinction between 1 and 2 is `make -e` command-line switch.
>
> Thanks
>
Thanks for your help and support.
I created a new pull request in google/vbootrom and waiting for google team review.
Hao,
Could you please help to review it?
https://github.com/google/vbootrom/pull/10
Thanks-Jamin
> /mjt
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-28 7:41 ` Jamin Lin via
@ 2025-07-29 9:12 ` Cédric Le Goater
2025-07-30 1:47 ` Jamin Lin via
0 siblings, 1 reply; 61+ messages in thread
From: Cédric Le Goater @ 2025-07-29 9:12 UTC (permalink / raw)
To: Jamin Lin, Michael Tokarev, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Hao Wu, Havard Skinnemoen
Michael, Jamin,
On 7/28/25 09:41, Jamin Lin wrote:
> Hi Michael, Cédric
>
>> From: Michael Tokarev <mjt@tls.msk.ru>
>> Sent: Monday, July 28, 2025 3:12 PM
>> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater <clg@kaod.org>;
>> Peter Maydell <peter.maydell@linaro.org>; Steven Lee
>> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Andrew
>> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
>> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
>> <qemu-devel@nongnu.org>
>> Cc: Troy Lee <troy_lee@aspeedtech.com>; Hao Wu <wuhaotsh@google.com>;
>> Havard Skinnemoen <hskinnemoen@google.com>
>> Subject: Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP
>> SCU initialization support
>>
>> On 28.07.2025 10:02, Jamin Lin wrote:
>>
>>> It seems this patch fix this issue,
>>> https://patchwork.kernel.org/project/qemu-devel/patch/607a943a587248fb
>>> e0ff0897de80aee98a093caa.1753654515.git.mjt@tls.msk.ru/
>>
>> Yeah, I posted that patch yesterday after realizing our roms/vbootrom
>> submodule is outdated.
>>
>>> Do I need to update vbootrom/ast27x0/Makefile?
>>> I set "?=" to make user able to set variables in the command line.
>>
>> The prob with `CC ?=` construct is that CC variable is always set by make, so
>> this line becomes useless. The question mark should be removed, that's all.
>>
>>> 1.
>>> export CC=aarch64-linux-gnu-gcc
>>> make
>>> 2. make CC=aarch64-linux-gnu-gcc
>>>
>>> 3. Update Make file and user only need to issue "make"
>>
>> See how it's done in other subdirs of vbootrom. You only need to remove ?
>> from CC variable assignment.
>>
>> Distinction between 1 and 2 is `make -e` command-line switch.
>>
>> Thanks
>>
> Thanks for your help and support.
> I created a new pull request in google/vbootrom and waiting for google team review.
> Hao,
> Could you please help to review it?
> https://github.com/google/vbootrom/pull/10
>
The vbootrom PR was merged (commit 183c9ff8056b).
Could you please update and resend :
https://lore.kernel.org/qemu-devel/2a89ad4c8f5665d07952a4f1749caa6ec0cd3d9c.1753654515.git.mjt@tls.msk.ru/
Thanks,
C.
^ permalink raw reply [flat|nested] 61+ messages in thread
* RE: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-29 9:12 ` Cédric Le Goater
@ 2025-07-30 1:47 ` Jamin Lin via
2025-07-30 4:59 ` Cédric Le Goater
0 siblings, 1 reply; 61+ messages in thread
From: Jamin Lin via @ 2025-07-30 1:47 UTC (permalink / raw)
To: Cédric Le Goater, Michael Tokarev, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Hao Wu, Havard Skinnemoen
Hi Cédric, Michael
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Tuesday, July 29, 2025 5:12 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Michael Tokarev
> <mjt@tls.msk.ru>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Andrew
> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Hao Wu <wuhaotsh@google.com>;
> Havard Skinnemoen <hskinnemoen@google.com>
> Subject: Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP
> SCU initialization support
>
> Michael, Jamin,
>
> On 7/28/25 09:41, Jamin Lin wrote:
> > Hi Michael, Cédric
> >
> >> From: Michael Tokarev <mjt@tls.msk.ru>
> >> Sent: Monday, July 28, 2025 3:12 PM
> >> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater
> >> <clg@kaod.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee
> >> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Andrew
> >> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
> >> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
> >> here <qemu-devel@nongnu.org>
> >> Cc: Troy Lee <troy_lee@aspeedtech.com>; Hao Wu
> <wuhaotsh@google.com>;
> >> Havard Skinnemoen <hskinnemoen@google.com>
> >> Subject: Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with
> >> SSP/TSP SCU initialization support
> >>
> >> On 28.07.2025 10:02, Jamin Lin wrote:
> >>
> >>> It seems this patch fix this issue,
> >>> https://patchwork.kernel.org/project/qemu-devel/patch/607a943a587248
> >>> fb e0ff0897de80aee98a093caa.1753654515.git.mjt@tls.msk.ru/
> >>
> >> Yeah, I posted that patch yesterday after realizing our roms/vbootrom
> >> submodule is outdated.
> >>
> >>> Do I need to update vbootrom/ast27x0/Makefile?
> >>> I set "?=" to make user able to set variables in the command line.
> >>
> >> The prob with `CC ?=` construct is that CC variable is always set by
> >> make, so this line becomes useless. The question mark should be removed,
> that's all.
> >>
> >>> 1.
> >>> export CC=aarch64-linux-gnu-gcc
> >>> make
> >>> 2. make CC=aarch64-linux-gnu-gcc
> >>>
> >>> 3. Update Make file and user only need to issue "make"
> >>
> >> See how it's done in other subdirs of vbootrom. You only need to remove ?
> >> from CC variable assignment.
> >>
> >> Distinction between 1 and 2 is `make -e` command-line switch.
> >>
> >> Thanks
> >>
> > Thanks for your help and support.
> > I created a new pull request in google/vbootrom and waiting for google team
> review.
> > Hao,
> > Could you please help to review it?
> > https://github.com/google/vbootrom/pull/10
> >
> The vbootrom PR was merged (commit 183c9ff8056b).
>
> Could you please update and resend :
>
>
> https://lore.kernel.org/qemu-devel/2a89ad4c8f5665d07952a4f1749caa6ec0cd
> 3d9c.1753654515.git.mjt@tls.msk.ru/
>
Resend patch here, https://patchwork.kernel.org/project/qemu-devel/patch/20250730013406.3847667-1-jamin_lin@aspeedtech.com/
Thanks-Jamin
> Thanks,
>
> C.
>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-30 1:47 ` Jamin Lin via
@ 2025-07-30 4:59 ` Cédric Le Goater
0 siblings, 0 replies; 61+ messages in thread
From: Cédric Le Goater @ 2025-07-30 4:59 UTC (permalink / raw)
To: Jamin Lin, Michael Tokarev, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Hao Wu, Havard Skinnemoen
Jamin,
On 7/30/25 03:47, Jamin Lin wrote:
> Hi Cédric, Michael
>
>> From: Cédric Le Goater <clg@kaod.org>
>> Sent: Tuesday, July 29, 2025 5:12 PM
>> To: Jamin Lin <jamin_lin@aspeedtech.com>; Michael Tokarev
>> <mjt@tls.msk.ru>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee
>> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Andrew
>> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
>> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
>> <qemu-devel@nongnu.org>
>> Cc: Troy Lee <troy_lee@aspeedtech.com>; Hao Wu <wuhaotsh@google.com>;
>> Havard Skinnemoen <hskinnemoen@google.com>
>> Subject: Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP
>> SCU initialization support
>>
>> Michael, Jamin,
>>
>> On 7/28/25 09:41, Jamin Lin wrote:
>>> Hi Michael, Cédric
>>>
>>>> From: Michael Tokarev <mjt@tls.msk.ru>
>>>> Sent: Monday, July 28, 2025 3:12 PM
>>>> To: Jamin Lin <jamin_lin@aspeedtech.com>; Cédric Le Goater
>>>> <clg@kaod.org>; Peter Maydell <peter.maydell@linaro.org>; Steven Lee
>>>> <steven_lee@aspeedtech.com>; Troy Lee <leetroy@gmail.com>; Andrew
>>>> Jeffery <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>;
>>>> open list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC
>>>> here <qemu-devel@nongnu.org>
>>>> Cc: Troy Lee <troy_lee@aspeedtech.com>; Hao Wu
>> <wuhaotsh@google.com>;
>>>> Havard Skinnemoen <hskinnemoen@google.com>
>>>> Subject: Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with
>>>> SSP/TSP SCU initialization support
>>>>
>>>> On 28.07.2025 10:02, Jamin Lin wrote:
>>>>
>>>>> It seems this patch fix this issue,
>>>>> https://patchwork.kernel.org/project/qemu-devel/patch/607a943a587248
>>>>> fb e0ff0897de80aee98a093caa.1753654515.git.mjt@tls.msk.ru/
>>>>
>>>> Yeah, I posted that patch yesterday after realizing our roms/vbootrom
>>>> submodule is outdated.
>>>>
>>>>> Do I need to update vbootrom/ast27x0/Makefile?
>>>>> I set "?=" to make user able to set variables in the command line.
>>>>
>>>> The prob with `CC ?=` construct is that CC variable is always set by
>>>> make, so this line becomes useless. The question mark should be removed,
>> that's all.
>>>>
>>>>> 1.
>>>>> export CC=aarch64-linux-gnu-gcc
>>>>> make
>>>>> 2. make CC=aarch64-linux-gnu-gcc
>>>>>
>>>>> 3. Update Make file and user only need to issue "make"
>>>>
>>>> See how it's done in other subdirs of vbootrom. You only need to remove ?
>>>> from CC variable assignment.
>>>>
>>>> Distinction between 1 and 2 is `make -e` command-line switch.
>>>>
>>>> Thanks
>>>>
>>> Thanks for your help and support.
>>> I created a new pull request in google/vbootrom and waiting for google team
>> review.
>>> Hao,
>>> Could you please help to review it?
>>> https://github.com/google/vbootrom/pull/10
>>>
>> The vbootrom PR was merged (commit 183c9ff8056b).
>>
>> Could you please update and resend :
>>
>>
>> https://lore.kernel.org/qemu-devel/2a89ad4c8f5665d07952a4f1749caa6ec0cd
>> 3d9c.1753654515.git.mjt@tls.msk.ru/
>>
>
> Resend patch here, https://patchwork.kernel.org/project/qemu-devel/patch/20250730013406.3847667-1-jamin_lin@aspeedtech.com/
I had sent a larger update already. I copied you on v3.
Thanks,
C.
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-28 6:49 ` Cédric Le Goater
2025-07-28 7:02 ` Jamin Lin via
@ 2025-07-28 8:32 ` Michael Tokarev
2025-07-28 8:40 ` Cédric Le Goater
1 sibling, 1 reply; 61+ messages in thread
From: Michael Tokarev @ 2025-07-28 8:32 UTC (permalink / raw)
To: Cédric Le Goater, Jamin Lin, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Hao Wu, Havard Skinnemoen
On 28.07.2025 09:49, Cédric Le Goater wrote:
>> Please add build instructions to roms/Makefile. I dunno how this one is
>> related to roms/vbootrom which is already used for npcmxxx_bootrom.bin
>> files - maybe all the 3 bootroms should be kept in sync.
>
> I think they are relatively independent. Each has its own directory.
They can't be independent, from qemu PoV anyway, since both comes from
the same submodule (roms/vbootrom), - we can't update individual subdirs
in a submodule, we can update either whole submodule or not at all.
Thanks,
/mjt
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support
2025-07-28 8:32 ` Michael Tokarev
@ 2025-07-28 8:40 ` Cédric Le Goater
0 siblings, 0 replies; 61+ messages in thread
From: Cédric Le Goater @ 2025-07-28 8:40 UTC (permalink / raw)
To: Michael Tokarev, Jamin Lin, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, Hao Wu, Havard Skinnemoen
On 7/28/25 10:32, Michael Tokarev wrote:
> On 28.07.2025 09:49, Cédric Le Goater wrote:
>
>>> Please add build instructions to roms/Makefile. I dunno how this one is
>>> related to roms/vbootrom which is already used for npcmxxx_bootrom.bin
>>> files - maybe all the 3 bootroms should be kept in sync.
>>
>> I think they are relatively independent. Each has its own directory.
>
> They can't be independent, from qemu PoV anyway, since both comes from
> the same submodule (roms/vbootrom), - we can't update individual subdirs
> in a submodule, we can update either whole submodule or not at all.
yes. Updating the vbootrom submodule to the latest shouldn't be an issue
for the Nuvoton's images. We should do that when the fix for the aspeed
Makefile is pulled in.
Thanks,
C.
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v1 20/21] tests/function/aspeed: Replace manual loader with vbootrom for ast2700fc test
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (18 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 21/21] docs: Add support vbootrom for ast2700fc Jamin Lin via
2025-07-17 5:22 ` [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
SSP and TSP now boot in a powered-off state by default. Enabling them requires
the PSP (Cortex-A35) to explicitly set SCU control registers at runtime. This
behavior aligns with real hardware.
However, the current functional test framework design does not support switching
the active VM console after launch. For example, when the PSP is launched first
to enable SSP via SCU, the test framework cannot dynamically attach to the SSP
console afterward to verify its behavior.
Due to this limitation, the test case for AST2700FC has been modified to use
vBootROM (`ast27x0_bootrom.bin`) instead of manually loading boot images and
firmwares via `-device loader`. The vBootROM integrates boot sequencing for
PSP, TSP, and SSP and sets up SCU configuration as part of its flow, enabling
more realistic full-system testing without relying on console switching.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
.../test_aarch64_aspeed_ast2700fc.py | 47 +------------------
1 file changed, 1 insertion(+), 46 deletions(-)
diff --git a/tests/functional/test_aarch64_aspeed_ast2700fc.py b/tests/functional/test_aarch64_aspeed_ast2700fc.py
index b85370e182..d7d50eda4d 100755
--- a/tests/functional/test_aarch64_aspeed_ast2700fc.py
+++ b/tests/functional/test_aarch64_aspeed_ast2700fc.py
@@ -72,52 +72,7 @@ def do_ast2700fc_tsp_test(self):
'[72c02000] 06010103')
def start_ast2700fc_test(self, name):
- ca35_core = 4
- uboot_size = os.path.getsize(self.scratch_file(name,
- 'u-boot-nodtb.bin'))
- uboot_dtb_load_addr = hex(0x400000000 + uboot_size)
-
- load_images_list = [
- {
- 'addr': '0x400000000',
- 'file': self.scratch_file(name,
- 'u-boot-nodtb.bin')
- },
- {
- 'addr': str(uboot_dtb_load_addr),
- 'file': self.scratch_file(name, 'u-boot.dtb')
- },
- {
- 'addr': '0x430000000',
- 'file': self.scratch_file(name, 'bl31.bin')
- },
- {
- 'addr': '0x430080000',
- 'file': self.scratch_file(name, 'optee',
- 'tee-raw.bin')
- }
- ]
-
- for load_image in load_images_list:
- addr = load_image['addr']
- file = load_image['file']
- self.vm.add_args('-device',
- f'loader,force-raw=on,addr={addr},file={file}')
-
- for i in range(ca35_core):
- self.vm.add_args('-device',
- f'loader,addr=0x430000000,cpu-num={i}')
-
- load_elf_list = {
- 'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'),
- 'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf')
- }
-
- for cpu_num, key in enumerate(load_elf_list, start=4):
- file = load_elf_list[key]
- self.vm.add_args('-device',
- f'loader,file={file},cpu-num={cpu_num}')
-
+ self.vm.add_args('-bios', 'ast27x0_bootrom.bin')
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* [PATCH v1 21/21] docs: Add support vbootrom for ast2700fc
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (19 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 20/21] tests/function/aspeed: Replace manual loader with vbootrom for ast2700fc test Jamin Lin via
@ 2025-07-17 3:40 ` Jamin Lin via
2025-07-17 5:22 ` [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin via @ 2025-07-17 3:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
docs/system/arm/aspeed.rst | 41 ++++++++++++++++++++++++++++++++------
1 file changed, 35 insertions(+), 6 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index bf18c56347..bc836e486f 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -1,4 +1,4 @@
-Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
+Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
====================================================================================================================================================================================================================================================================================================================================================================================================================================
The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
@@ -243,7 +243,7 @@ under Linux), use :
-M ast2500-evb,bmc-console=uart3
-Aspeed 2700 family boards (``ast2700-evb``)
+Aspeed 2700 family boards (``ast2700-evb``, ``ast2700fc``)
==================================================================
The QEMU Aspeed machines model BMCs of Aspeed evaluation boards.
@@ -360,6 +360,14 @@ Booting the ast2700fc machine
AST2700 features four Cortex-A35 primary processors and two Cortex-M4 coprocessors.
**ast2700-evb** machine focuses on emulating the four Cortex-A35 primary processors,
**ast2700fc** machine extends **ast2700-evb** by adding support for the two Cortex-M4 coprocessors.
+There are two methods to boot the ast2700fc machine.
+
+Manual boot using ``-device loader``:
+
+In this approach, users manually load firmware and assign entry points via QEMU loader devices.
+By default, the PSP begins execution at address ``0x430000000``, the load address of the bl31
+firmware. The SSP and TSP start in the powered-off state and must be explicitly enabled by the
+PSP through writes to SCU registers.
Steps to boot the AST2700fc machine:
@@ -370,8 +378,8 @@ Steps to boot the AST2700fc machine:
* bl31.bin
* optee/tee-raw.bin
* image-bmc
- * zephyr-aspeed-ssp.elf (for SSP firmware, CPU 5)
- * zephyr-aspeed-tsp.elf (for TSP firmware, CPU 6)
+ * zephyr-aspeed-ssp.bin (for SSP firmware, CPU 5)
+ * zephyr-aspeed-tsp.bin (for TSP firmware, CPU 6)
2. Execute the following command to start ``ast2700fc`` machine:
@@ -385,17 +393,38 @@ Steps to boot the AST2700fc machine:
-device loader,force-raw=on,addr=$((0x400000000 + ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb \
-device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
-device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/optee/tee-raw.bin \
+ -device loader,addr=0x42C000000,file=${IMGDIR}/zephyr-aspeed-ssp.bin,force-raw=on \
+ -device loader,addr=0x42E000000,file=${IMGDIR}/zephyr-aspeed-tsp.bin,force-raw=on \
-device loader,cpu-num=0,addr=0x430000000 \
-device loader,cpu-num=1,addr=0x430000000 \
-device loader,cpu-num=2,addr=0x430000000 \
-device loader,cpu-num=3,addr=0x430000000 \
-drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
- -device loader,file=${IMGDIR}/zephyr-aspeed-ssp.elf,cpu-num=4 \
- -device loader,file=${IMGDIR}/zephyr-aspeed-tsp.elf,cpu-num=5 \
-serial pty -serial pty -serial pty \
-snapshot \
-S -nographic
+Boot using a virtual boot ROM (-bios):
+
+In this method, the virtual boot ROM (vbootrom) handles the full initialization sequence.
+It starts the PSP, which then enables the SSP and TSP by programming the appropriate SCU
+registers, following the hardware behavior.
+
+Execute the following command to start ``ast2700fc`` machine:
+
+.. code-block:: bash
+
+ IMGDIR=ast2700-default
+
+ $ qemu-system-aarch64 -M ast2700fc \
+ -bios ast27x0_bootrom.bin \
+ -drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
+ -serial pty -serial pty -serial pty \
+ -snapshot \
+ -S -nographic
+
+Serial Console Redirection:
+
After launching QEMU, serial devices will be automatically redirected.
Example output:
--
2.43.0
^ permalink raw reply related [flat|nested] 61+ messages in thread* RE: [PATCH v1 00/21] Control coprocessor reset for AST2700
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
` (20 preceding siblings ...)
2025-07-17 3:40 ` [PATCH v1 21/21] docs: Add support vbootrom for ast2700fc Jamin Lin via
@ 2025-07-17 5:22 ` Jamin Lin
21 siblings, 0 replies; 61+ messages in thread
From: Jamin Lin @ 2025-07-17 5:22 UTC (permalink / raw)
To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee,
Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee
All,
> Subject: [PATCH v1 00/21] Control coprocessor reset for AST2700
>
> v1
> - Added support for Vboot ROM.
> - Moved coprocessor initialization from machine level to SoC level
> - Unified SCU controllers between PSP and coprocessors
> - Shared the same SRAM between PSP and coprocessors
> - Support PSP DRAM remaps coprocessor SDRAM
> - Added support for controlling coprocessor reset via SCU registers.
>
Lost to add the following info:
This patch series depends on this path,
https://patchwork.kernel.org/project/qemu-devel/patch/20250715061904.97540-1-clg@redhat.com/
QEMU version:
https://github.com/qemu/qemu/commit/f96b157ebb93f94cd56ebbc99bc20982b8fd86ef
Jamin
> Jamin Lin (21):
> hw/arm/aspeed_ast27x0-fc: Support VBootRom
> hw/arm/ast27x0: Move SSP coprocessor initialization from machine to
> SoC leve
> hw/arm/ast27x0: Move TSP coprocessor initialization from machine to
> SoC leve
> hw/arm/aspeed_ast27x0-ssp: Switch SSP memory to SDRAM and use
> dram_container for remap support
> hw/arm/aspeed_ast27x0-tsp: Switch TSP memory to SDRAM and use
> dram_container for remap support
> hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device
> realization order
> hw/arm/ast27x0: Add SRAM alias for TSP and ensure correct device
> realization order
> hw/arm/ast27x0: Add SCU alias for SSP and ensure correct device
> realization order
> hw/arm/ast27x0: Add SCU alias for TSP and ensure correct device
> realization order
> hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support
> memory aliasing
> hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap and update
> realization order
> hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap and update
> realization order
> hw/arm/ast27x0: Start SSP in powered-off state to match hardware
> behavior
> hw/arm/ast27x0: Start TSP in powered-off state to match hardware
> behavior
> hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap
> hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap
> hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU
> registers
> hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU
> registers
> pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization
> support
> tests/function/aspeed: Replace manual loader with vbootrom for
> ast2700fc test
> docs: Add support vbootrom for ast2700fc
>
> docs/system/arm/aspeed.rst | 41 +++-
> include/hw/arm/aspeed_soc.h | 48 +++--
> include/hw/misc/aspeed_scu.h | 4 +
> hw/arm/aspeed_ast27x0-fc.c | 133 +++++++-----
> hw/arm/aspeed_ast27x0-ssp.c | 46 +++--
> hw/arm/aspeed_ast27x0-tsp.c | 43 ++--
> hw/arm/aspeed_ast27x0.c | 188
> +++++++++++++++--
> hw/misc/aspeed_scu.c | 194
> +++++++++++++++++-
> pc-bios/ast27x0_bootrom.bin | Bin 15552 -> 17192
> bytes
> .../test_aarch64_aspeed_ast2700fc.py | 47 +----
> 10 files changed, 562 insertions(+), 182 deletions(-)
>
> --
> 2.43.0
^ permalink raw reply [flat|nested] 61+ messages in thread