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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dc565d62dsm10420009f8f.93.2025.02.10.00.47.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Feb 2025 00:47:05 -0800 (PST) Message-ID: <07a12390-dea8-49dd-a38e-13aecddc6b87@redhat.com> Date: Mon, 10 Feb 2025 09:47:04 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] hw/arm/smmuv3: Move reset to exit phase Content-Language: en-US To: Peter Maydell , Peter Xu Cc: eric.auger.pro@gmail.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, mst@redhat.com, jasowang@redhat.com, imammedo@redhat.com, alex.williamson@redhat.com, clg@redhat.com, philmd@linaro.org, zhenzhong.duan@intel.com, ddutile@redhat.com References: <20250206142307.921070-1-eric.auger@redhat.com> <20250206142307.921070-5-eric.auger@redhat.com> <7102d470-ac72-4c02-b8bc-20f1379a4843@redhat.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.405, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Peter, On 2/7/25 7:18 PM, Peter Maydell wrote: > On Fri, 7 Feb 2025 at 17:48, Peter Xu wrote: >> On Fri, Feb 07, 2025 at 04:58:39PM +0000, Peter Maydell wrote: >>> (I wonder if we ought to suggest quiescing outstanding >>> DMA in the enter phase? But it's probably easier to fix >>> the iommus like this series does than try to get every >>> dma-capable pci device to do something different.) >> I wonder if we should provide some generic helper to register vIOMMU reset >> callbacks, so that we'll be sure any vIOMMU model impl that will register >> at exit() phase only, and do nothing during the initial two phases. Then >> we can put some rich comment on that helper on why. >> >> Looks like it means the qemu reset model in the future can be a combination >> of device tree (which resets depth-first) and the three phases model. We >> will start to use different approach to solve different problems. > The tree of QOM devices (i.e. the one based on the qbus buses > and rooted at the sysbus) resets depth-first, but it does so in > three phases: first we traverse everything doing 'enter'; then > we traverse everything doing 'hold'; then we traverse everything > doing 'exit'. There *used* to be an awkward mix of some things > being three-phase and some not, but we have now got rid of all > of those so a system reset does a single three-phase reset run > which resets everything. Thank you Peter. This is reassuring. I will add such kind of description in the commit msg/cover letter. Eric > > -- PMM >