From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair23@gmail.com>,
Frank Chang <frank.chang@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Chih-Min Chao <chihmin.chao@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Kito Cheng <kito.cheng@sifive.com>
Subject: Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store
Date: Thu, 21 Oct 2021 16:28:15 -0700 [thread overview]
Message-ID: <07a1c82b-a8d1-cb01-e647-e777cb3aa497@linaro.org> (raw)
In-Reply-To: <CAKmqyKM7kf7mFrh6i33ZSbLtf6tLC=qSUmzRTvwk=H_rFYs3ZA@mail.gmail.com>
On 10/21/21 3:31 PM, Alistair Francis wrote:
> On Fri, Oct 22, 2021 at 2:30 AM <frank.chang@sifive.com> wrote:
>>
>> From: Kito Cheng <kito.cheng@sifive.com>
>>
>> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
>> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
>> Signed-off-by: Frank Chang <frank.chang@sifive.com>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> It doesn't look like this made it through to the list. I only see v3
> on patchew: https://patchew.org/QEMU/20211016090742.3034669-1-frank.chang@sifive.com/
It's just the cover-letter that got lost.
https://lore.kernel.org/qemu-devel/20211021162956.2772656-2-frank.chang@sifive.com/
> Can you rebase this on
> https://github.com/alistair23/qemu/tree/riscv-to-apply.next when you
> re-send it?
But a rebase is probably required anyway.
r~
next prev parent reply other threads:[~2021-10-21 23:29 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20211021162956.2772656-1-frank.chang@sifive.com>
2021-10-21 16:29 ` [PATCH v5 1/8] target/riscv: zfh: half-precision load and store frank.chang
2021-10-21 22:01 ` Alistair Francis
2021-10-21 22:31 ` Alistair Francis
2021-10-21 23:28 ` Richard Henderson [this message]
2021-10-22 3:25 ` Frank Chang
2021-10-21 16:29 ` [PATCH v5 2/8] target/riscv: zfh: half-precision computational frank.chang
2021-10-21 16:29 ` [PATCH v5 3/8] target/riscv: zfh: half-precision convert and move frank.chang
2021-10-21 16:29 ` [PATCH v5 4/8] target/riscv: zfh: half-precision floating-point compare frank.chang
2021-10-21 16:29 ` [PATCH v5 5/8] target/riscv: zfh: half-precision floating-point classify frank.chang
2021-10-21 16:29 ` [PATCH v5 6/8] target/riscv: zfh: add Zfh cpu property frank.chang
2021-10-21 16:29 ` [PATCH v5 7/8] target/riscv: zfh: implement zfhmin extension frank.chang
2021-10-21 16:29 ` [PATCH v5 8/8] target/riscv: zfh: add Zfhmin cpu property frank.chang
2021-11-02 14:07 ` [PATCH v5 0/8] target/riscv: support Zfh, Zfhmin extension v0.1 Frank Chang
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