* [PATCH v5 1/8] target/riscv: zfh: half-precision load and store
[not found] <20211021162956.2772656-1-frank.chang@sifive.com>
@ 2021-10-21 16:29 ` frank.chang
2021-10-21 22:01 ` Alistair Francis
2021-10-21 22:31 ` Alistair Francis
2021-10-21 16:29 ` [PATCH v5 2/8] target/riscv: zfh: half-precision computational frank.chang
` (7 subsequent siblings)
8 siblings, 2 replies; 13+ messages in thread
From: frank.chang @ 2021-10-21 16:29 UTC (permalink / raw)
To: qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, qemu-devel,
Chih-Min Chao, Palmer Dabbelt, Alistair Francis, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.h | 1 +
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvzfh.c.inc | 65 +++++++++++++++++++++++
target/riscv/translate.c | 8 +++
4 files changed, 78 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvzfh.c.inc
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a33dc30be81..da3c436987c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -299,6 +299,7 @@ struct RISCVCPU {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_zfh;
char *priv_spec;
char *user_spec;
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2f251dac1bb..b36a3d8dbf8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -726,3 +726,7 @@ binv 0110100 .......... 001 ..... 0110011 @r
binvi 01101. ........... 001 ..... 0010011 @sh
bset 0010100 .......... 001 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
+
+# *** RV32 Zfh Extension ***
+flh ............ ..... 001 ..... 0000111 @i
+fsh ....... ..... ..... 001 ..... 0100111 @s
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
new file mode 100644
index 00000000000..dad1d703d72
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -0,0 +1,65 @@
+/*
+ * RISC-V translation routines for the RV64Zfh Standard Extension.
+ *
+ * Copyright (c) 2020 Chih-Min Chao, chihmin.chao@sifive.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define REQUIRE_ZFH(ctx) do { \
+ if (!ctx->ext_zfh) { \
+ return false; \
+ } \
+} while (0)
+
+static bool trans_flh(DisasContext *ctx, arg_flh *a)
+{
+ TCGv_i64 dest;
+ TCGv t0;
+
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ t0 = get_gpr(ctx, a->rs1, EXT_NONE);
+ if (a->imm) {
+ TCGv temp = temp_new(ctx);
+ tcg_gen_addi_tl(temp, t0, a->imm);
+ t0 = temp;
+ }
+
+ dest = cpu_fpr[a->rd];
+ tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TEUW);
+ gen_nanbox_h(dest, dest);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
+{
+ TCGv t0;
+
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ t0 = get_gpr(ctx, a->rs1, EXT_NONE);
+ if (a->imm) {
+ TCGv temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, t0, a->imm);
+ t0 = temp;
+ }
+
+ tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW);
+
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d38f87d7188..ad963d1898f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -70,6 +70,7 @@ typedef struct DisasContext {
RISCVMXL ol;
bool virt_enabled;
bool ext_ifencei;
+ bool ext_zfh;
bool hlsx;
/* vector extension */
bool vill;
@@ -127,6 +128,11 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
}
+static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
+{
+ tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48));
+}
+
/*
* A narrow n-bit operation, where n < FLEN, checks that input operands
* are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
@@ -550,6 +556,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
#include "insn_trans/trans_rvh.c.inc"
#include "insn_trans/trans_rvv.c.inc"
#include "insn_trans/trans_rvb.c.inc"
+#include "insn_trans/trans_rvzfh.c.inc"
#include "insn_trans/trans_privileged.c.inc"
/* Include the auto-generated decoder for 16 bit insn */
@@ -602,6 +609,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->misa_ext = env->misa_ext;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
+ ctx->ext_zfh = cpu->cfg.ext_zfh;
ctx->vlen = cpu->cfg.vlen;
ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store
2021-10-21 16:29 ` [PATCH v5 1/8] target/riscv: zfh: half-precision load and store frank.chang
@ 2021-10-21 22:01 ` Alistair Francis
2021-10-21 22:31 ` Alistair Francis
1 sibling, 0 replies; 13+ messages in thread
From: Alistair Francis @ 2021-10-21 22:01 UTC (permalink / raw)
To: Frank Chang
Cc: open list:RISC-V, Bin Meng, Richard Henderson,
qemu-devel@nongnu.org Developers, Chih-Min Chao, Palmer Dabbelt,
Alistair Francis, Kito Cheng
On Fri, Oct 22, 2021 at 2:30 AM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode | 4 ++
> target/riscv/insn_trans/trans_rvzfh.c.inc | 65 +++++++++++++++++++++++
> target/riscv/translate.c | 8 +++
> 4 files changed, 78 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rvzfh.c.inc
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index a33dc30be81..da3c436987c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -299,6 +299,7 @@ struct RISCVCPU {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_zfh;
>
> char *priv_spec;
> char *user_spec;
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 2f251dac1bb..b36a3d8dbf8 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -726,3 +726,7 @@ binv 0110100 .......... 001 ..... 0110011 @r
> binvi 01101. ........... 001 ..... 0010011 @sh
> bset 0010100 .......... 001 ..... 0110011 @r
> bseti 00101. ........... 001 ..... 0010011 @sh
> +
> +# *** RV32 Zfh Extension ***
> +flh ............ ..... 001 ..... 0000111 @i
> +fsh ....... ..... ..... 001 ..... 0100111 @s
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
> new file mode 100644
> index 00000000000..dad1d703d72
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
> @@ -0,0 +1,65 @@
> +/*
> + * RISC-V translation routines for the RV64Zfh Standard Extension.
> + *
> + * Copyright (c) 2020 Chih-Min Chao, chihmin.chao@sifive.com
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_ZFH(ctx) do { \
> + if (!ctx->ext_zfh) { \
> + return false; \
> + } \
> +} while (0)
> +
> +static bool trans_flh(DisasContext *ctx, arg_flh *a)
> +{
> + TCGv_i64 dest;
> + TCGv t0;
> +
> + REQUIRE_FPU;
> + REQUIRE_ZFH(ctx);
> +
> + t0 = get_gpr(ctx, a->rs1, EXT_NONE);
> + if (a->imm) {
> + TCGv temp = temp_new(ctx);
> + tcg_gen_addi_tl(temp, t0, a->imm);
> + t0 = temp;
> + }
> +
> + dest = cpu_fpr[a->rd];
> + tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TEUW);
> + gen_nanbox_h(dest, dest);
> +
> + mark_fs_dirty(ctx);
> + return true;
> +}
> +
> +static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
> +{
> + TCGv t0;
> +
> + REQUIRE_FPU;
> + REQUIRE_ZFH(ctx);
> +
> + t0 = get_gpr(ctx, a->rs1, EXT_NONE);
> + if (a->imm) {
> + TCGv temp = tcg_temp_new();
> + tcg_gen_addi_tl(temp, t0, a->imm);
> + t0 = temp;
> + }
> +
> + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW);
> +
> + return true;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index d38f87d7188..ad963d1898f 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -70,6 +70,7 @@ typedef struct DisasContext {
> RISCVMXL ol;
> bool virt_enabled;
> bool ext_ifencei;
> + bool ext_zfh;
> bool hlsx;
> /* vector extension */
> bool vill;
> @@ -127,6 +128,11 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
> tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
> }
>
> +static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
> +{
> + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48));
> +}
> +
> /*
> * A narrow n-bit operation, where n < FLEN, checks that input operands
> * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
> @@ -550,6 +556,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> #include "insn_trans/trans_rvh.c.inc"
> #include "insn_trans/trans_rvv.c.inc"
> #include "insn_trans/trans_rvb.c.inc"
> +#include "insn_trans/trans_rvzfh.c.inc"
> #include "insn_trans/trans_privileged.c.inc"
>
> /* Include the auto-generated decoder for 16 bit insn */
> @@ -602,6 +609,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->misa_ext = env->misa_ext;
> ctx->frm = -1; /* unknown rounding mode */
> ctx->ext_ifencei = cpu->cfg.ext_ifencei;
> + ctx->ext_zfh = cpu->cfg.ext_zfh;
> ctx->vlen = cpu->cfg.vlen;
> ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
> ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store
2021-10-21 16:29 ` [PATCH v5 1/8] target/riscv: zfh: half-precision load and store frank.chang
2021-10-21 22:01 ` Alistair Francis
@ 2021-10-21 22:31 ` Alistair Francis
2021-10-21 23:28 ` Richard Henderson
1 sibling, 1 reply; 13+ messages in thread
From: Alistair Francis @ 2021-10-21 22:31 UTC (permalink / raw)
To: Frank Chang
Cc: open list:RISC-V, Bin Meng, Richard Henderson,
qemu-devel@nongnu.org Developers, Chih-Min Chao, Palmer Dabbelt,
Alistair Francis, Kito Cheng
On Fri, Oct 22, 2021 at 2:30 AM <frank.chang@sifive.com> wrote:
>
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
It doesn't look like this made it through to the list. I only see v3
on patchew: https://patchew.org/QEMU/20211016090742.3034669-1-frank.chang@sifive.com/
Can you rebase this on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next when you
re-send it?
Alistair
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/insn32.decode | 4 ++
> target/riscv/insn_trans/trans_rvzfh.c.inc | 65 +++++++++++++++++++++++
> target/riscv/translate.c | 8 +++
> 4 files changed, 78 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rvzfh.c.inc
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index a33dc30be81..da3c436987c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -299,6 +299,7 @@ struct RISCVCPU {
> bool ext_counters;
> bool ext_ifencei;
> bool ext_icsr;
> + bool ext_zfh;
>
> char *priv_spec;
> char *user_spec;
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 2f251dac1bb..b36a3d8dbf8 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -726,3 +726,7 @@ binv 0110100 .......... 001 ..... 0110011 @r
> binvi 01101. ........... 001 ..... 0010011 @sh
> bset 0010100 .......... 001 ..... 0110011 @r
> bseti 00101. ........... 001 ..... 0010011 @sh
> +
> +# *** RV32 Zfh Extension ***
> +flh ............ ..... 001 ..... 0000111 @i
> +fsh ....... ..... ..... 001 ..... 0100111 @s
> diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
> new file mode 100644
> index 00000000000..dad1d703d72
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
> @@ -0,0 +1,65 @@
> +/*
> + * RISC-V translation routines for the RV64Zfh Standard Extension.
> + *
> + * Copyright (c) 2020 Chih-Min Chao, chihmin.chao@sifive.com
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#define REQUIRE_ZFH(ctx) do { \
> + if (!ctx->ext_zfh) { \
> + return false; \
> + } \
> +} while (0)
> +
> +static bool trans_flh(DisasContext *ctx, arg_flh *a)
> +{
> + TCGv_i64 dest;
> + TCGv t0;
> +
> + REQUIRE_FPU;
> + REQUIRE_ZFH(ctx);
> +
> + t0 = get_gpr(ctx, a->rs1, EXT_NONE);
> + if (a->imm) {
> + TCGv temp = temp_new(ctx);
> + tcg_gen_addi_tl(temp, t0, a->imm);
> + t0 = temp;
> + }
> +
> + dest = cpu_fpr[a->rd];
> + tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, MO_TEUW);
> + gen_nanbox_h(dest, dest);
> +
> + mark_fs_dirty(ctx);
> + return true;
> +}
> +
> +static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
> +{
> + TCGv t0;
> +
> + REQUIRE_FPU;
> + REQUIRE_ZFH(ctx);
> +
> + t0 = get_gpr(ctx, a->rs1, EXT_NONE);
> + if (a->imm) {
> + TCGv temp = tcg_temp_new();
> + tcg_gen_addi_tl(temp, t0, a->imm);
> + t0 = temp;
> + }
> +
> + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUW);
> +
> + return true;
> +}
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index d38f87d7188..ad963d1898f 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -70,6 +70,7 @@ typedef struct DisasContext {
> RISCVMXL ol;
> bool virt_enabled;
> bool ext_ifencei;
> + bool ext_zfh;
> bool hlsx;
> /* vector extension */
> bool vill;
> @@ -127,6 +128,11 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
> tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
> }
>
> +static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
> +{
> + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48));
> +}
> +
> /*
> * A narrow n-bit operation, where n < FLEN, checks that input operands
> * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
> @@ -550,6 +556,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
> #include "insn_trans/trans_rvh.c.inc"
> #include "insn_trans/trans_rvv.c.inc"
> #include "insn_trans/trans_rvb.c.inc"
> +#include "insn_trans/trans_rvzfh.c.inc"
> #include "insn_trans/trans_privileged.c.inc"
>
> /* Include the auto-generated decoder for 16 bit insn */
> @@ -602,6 +609,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->misa_ext = env->misa_ext;
> ctx->frm = -1; /* unknown rounding mode */
> ctx->ext_ifencei = cpu->cfg.ext_ifencei;
> + ctx->ext_zfh = cpu->cfg.ext_zfh;
> ctx->vlen = cpu->cfg.vlen;
> ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
> ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store
2021-10-21 22:31 ` Alistair Francis
@ 2021-10-21 23:28 ` Richard Henderson
2021-10-22 3:25 ` Frank Chang
0 siblings, 1 reply; 13+ messages in thread
From: Richard Henderson @ 2021-10-21 23:28 UTC (permalink / raw)
To: Alistair Francis, Frank Chang
Cc: open list:RISC-V, Bin Meng, qemu-devel@nongnu.org Developers,
Chih-Min Chao, Palmer Dabbelt, Alistair Francis, Kito Cheng
On 10/21/21 3:31 PM, Alistair Francis wrote:
> On Fri, Oct 22, 2021 at 2:30 AM <frank.chang@sifive.com> wrote:
>>
>> From: Kito Cheng <kito.cheng@sifive.com>
>>
>> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
>> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
>> Signed-off-by: Frank Chang <frank.chang@sifive.com>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> It doesn't look like this made it through to the list. I only see v3
> on patchew: https://patchew.org/QEMU/20211016090742.3034669-1-frank.chang@sifive.com/
It's just the cover-letter that got lost.
https://lore.kernel.org/qemu-devel/20211021162956.2772656-2-frank.chang@sifive.com/
> Can you rebase this on
> https://github.com/alistair23/qemu/tree/riscv-to-apply.next when you
> re-send it?
But a rebase is probably required anyway.
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 1/8] target/riscv: zfh: half-precision load and store
2021-10-21 23:28 ` Richard Henderson
@ 2021-10-22 3:25 ` Frank Chang
0 siblings, 0 replies; 13+ messages in thread
From: Frank Chang @ 2021-10-22 3:25 UTC (permalink / raw)
To: Richard Henderson
Cc: Alistair Francis, open list:RISC-V, Bin Meng,
qemu-devel@nongnu.org Developers, Chih-Min Chao, Palmer Dabbelt,
Alistair Francis, Kito Cheng
[-- Attachment #1: Type: text/plain, Size: 1553 bytes --]
On Fri, Oct 22, 2021 at 7:28 AM Richard Henderson <
richard.henderson@linaro.org> wrote:
> On 10/21/21 3:31 PM, Alistair Francis wrote:
> > On Fri, Oct 22, 2021 at 2:30 AM <frank.chang@sifive.com> wrote:
> >>
> >> From: Kito Cheng <kito.cheng@sifive.com>
> >>
> >> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> >> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
> >> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> >
> > It doesn't look like this made it through to the list. I only see v3
> > on patchew:
> https://patchew.org/QEMU/20211016090742.3034669-1-frank.chang@sifive.com/
>
> It's just the cover-letter that got lost.
>
>
> https://lore.kernel.org/qemu-devel/20211021162956.2772656-2-frank.chang@sifive.com/
>
>
> > Can you rebase this on
> > https://github.com/alistair23/qemu/tree/riscv-to-apply.next when you
> > re-send it?
>
> But a rebase is probably required anyway.
>
Hi Alistair and Richard,
This patchset is already rebased on riscv-to-apply.next.
The Zfh and Zfhmin cpu properties are already moved to
/* Defaults for standard extensions */ section,
along with other Zi* extensions.
BTW, I found out my patchset won't appear at Patchew
if cover letter is only sent to qemu-riscv@nongnu.org.
(I used: "git send-email --to 'qemu-riscv@nongnu.org' ...",
instead of: "git send-email --to 'qemu-devel@nongnu.org,
qemu-riscv@nongnu.org' ...")
I will send it to qemu-devel@nongnu.org as well in my future patchset.
Regards,
Frank Chang
>
> r~
>
[-- Attachment #2: Type: text/html, Size: 3326 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 2/8] target/riscv: zfh: half-precision computational
[not found] <20211021162956.2772656-1-frank.chang@sifive.com>
2021-10-21 16:29 ` [PATCH v5 1/8] target/riscv: zfh: half-precision load and store frank.chang
@ 2021-10-21 16:29 ` frank.chang
2021-10-21 16:29 ` [PATCH v5 3/8] target/riscv: zfh: half-precision convert and move frank.chang
` (6 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: frank.chang @ 2021-10-21 16:29 UTC (permalink / raw)
To: qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, qemu-devel,
Chih-Min Chao, Palmer Dabbelt, Alistair Francis, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/fpu_helper.c | 86 +++++++++++++++
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode | 11 ++
target/riscv/insn_trans/trans_rvzfh.c.inc | 129 ++++++++++++++++++++++
target/riscv/internals.h | 16 +++
5 files changed, 255 insertions(+)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index d62f4709002..20bb89ad14f 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -81,6 +81,15 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
set_float_rounding_mode(softrm, &env->fp_status);
}
+static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
+ uint64_t rs3, int flags)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ float16 frs2 = check_nanbox_h(rs2);
+ float16 frs3 = check_nanbox_h(rs3);
+ return nanbox_h(float16_muladd(frs1, frs2, frs3, flags, &env->fp_status));
+}
+
static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
uint64_t rs3, int flags)
{
@@ -102,6 +111,12 @@ uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
return float64_muladd(frs1, frs2, frs3, 0, &env->fp_status);
}
+uint64_t helper_fmadd_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
+ uint64_t frs3)
+{
+ return do_fmadd_h(env, frs1, frs2, frs3, 0);
+}
+
uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
@@ -115,6 +130,12 @@ uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
&env->fp_status);
}
+uint64_t helper_fmsub_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
+ uint64_t frs3)
+{
+ return do_fmadd_h(env, frs1, frs2, frs3, float_muladd_negate_c);
+}
+
uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
@@ -128,6 +149,12 @@ uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
&env->fp_status);
}
+uint64_t helper_fnmsub_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
+ uint64_t frs3)
+{
+ return do_fmadd_h(env, frs1, frs2, frs3, float_muladd_negate_product);
+}
+
uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
uint64_t frs3)
{
@@ -142,6 +169,13 @@ uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
float_muladd_negate_product, &env->fp_status);
}
+uint64_t helper_fnmadd_h(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
+ uint64_t frs3)
+{
+ return do_fmadd_h(env, frs1, frs2, frs3,
+ float_muladd_negate_c | float_muladd_negate_product);
+}
+
uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
{
float32 frs1 = check_nanbox_s(rs1);
@@ -374,3 +408,55 @@ target_ulong helper_fclass_d(uint64_t frs1)
{
return fclass_d(frs1);
}
+
+uint64_t helper_fadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ float16 frs2 = check_nanbox_h(rs2);
+ return nanbox_h(float16_add(frs1, frs2, &env->fp_status));
+}
+
+uint64_t helper_fsub_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ float16 frs2 = check_nanbox_h(rs2);
+ return nanbox_h(float16_sub(frs1, frs2, &env->fp_status));
+}
+
+uint64_t helper_fmul_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ float16 frs2 = check_nanbox_h(rs2);
+ return nanbox_h(float16_mul(frs1, frs2, &env->fp_status));
+}
+
+uint64_t helper_fdiv_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ float16 frs2 = check_nanbox_h(rs2);
+ return nanbox_h(float16_div(frs1, frs2, &env->fp_status));
+}
+
+uint64_t helper_fmin_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ float16 frs2 = check_nanbox_h(rs2);
+ return nanbox_h(env->priv_ver < PRIV_VERSION_1_11_0 ?
+ float16_minnum(frs1, frs2, &env->fp_status) :
+ float16_minimum_number(frs1, frs2, &env->fp_status));
+}
+
+uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ float16 frs2 = check_nanbox_h(rs2);
+ return nanbox_h(env->priv_ver < PRIV_VERSION_1_11_0 ?
+ float16_maxnum(frs1, frs2, &env->fp_status) :
+ float16_maximum_number(frs1, frs2, &env->fp_status));
+}
+
+uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ return nanbox_h(float16_sqrt(frs1, &env->fp_status));
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c7a53762277..c6c0323fafc 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -7,12 +7,16 @@ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
/* Floating Point - fused */
DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
+DEF_HELPER_FLAGS_4(fmadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
+DEF_HELPER_FLAGS_4(fmsub_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fnmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fnmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
+DEF_HELPER_FLAGS_4(fnmsub_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fnmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(fnmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
+DEF_HELPER_FLAGS_4(fnmadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
/* Floating Point - Single Precision */
DEF_HELPER_FLAGS_3(fadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64)
@@ -62,6 +66,15 @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+/* Floating Point - Half Precision */
+DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
+DEF_HELPER_FLAGS_3(fsub_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
+DEF_HELPER_FLAGS_3(fmul_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
+DEF_HELPER_FLAGS_3(fdiv_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
+DEF_HELPER_FLAGS_3(fmin_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
+DEF_HELPER_FLAGS_3(fmax_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
+DEF_HELPER_FLAGS_2(fsqrt_h, TCG_CALL_NO_RWG, i64, env, i64)
+
/* Special functions */
DEF_HELPER_2(csrr, tl, env, int)
DEF_HELPER_3(csrw, void, env, int, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b36a3d8dbf8..66c231a3010 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -730,3 +730,14 @@ bseti 00101. ........... 001 ..... 0010011 @sh
# *** RV32 Zfh Extension ***
flh ............ ..... 001 ..... 0000111 @i
fsh ....... ..... ..... 001 ..... 0100111 @s
+fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm
+fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm
+fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm
+fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm
+fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm
+fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm
+fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm
+fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm
+fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm
+fmin_h 0010110 ..... ..... 000 ..... 1010011 @r
+fmax_h 0010110 ..... ..... 001 ..... 1010011 @r
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index dad1d703d72..9764d76f8bc 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -63,3 +63,132 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
return true;
}
+
+static bool trans_fmadd_h(DisasContext *ctx, arg_fmadd_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmadd_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmsub_h(DisasContext *ctx, arg_fmsub_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmsub_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fnmsub_h(DisasContext *ctx, arg_fnmsub_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmsub_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fnmadd_h(DisasContext *ctx, arg_fnmadd_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fnmadd_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2], cpu_fpr[a->rs3]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fadd_h(DisasContext *ctx, arg_fadd_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fadd_h(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsub_h(DisasContext *ctx, arg_fsub_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsub_h(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmul_h(DisasContext *ctx, arg_fmul_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fmul_h(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fdiv_h(DisasContext *ctx, arg_fdiv_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fdiv_h(cpu_fpr[a->rd], cpu_env,
+ cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsqrt_h(DisasContext *ctx, arg_fsqrt_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fsqrt_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmin_h(DisasContext *ctx, arg_fmin_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_helper_fmin_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_helper_fmax_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1],
+ cpu_fpr[a->rs2]);
+ mark_fs_dirty(ctx);
+ return true;
+}
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index b15ad394bb9..bce91da11a4 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -58,4 +58,20 @@ static inline float32 check_nanbox_s(uint64_t f)
}
}
+static inline uint64_t nanbox_h(float16 f)
+{
+ return f | MAKE_64BIT_MASK(16, 48);
+}
+
+static inline float16 check_nanbox_h(uint64_t f)
+{
+ uint64_t mask = MAKE_64BIT_MASK(16, 48);
+
+ if (likely((f & mask) == mask)) {
+ return (uint16_t)f;
+ } else {
+ return 0x7E00u; /* default qnan */
+ }
+}
+
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 3/8] target/riscv: zfh: half-precision convert and move
[not found] <20211021162956.2772656-1-frank.chang@sifive.com>
2021-10-21 16:29 ` [PATCH v5 1/8] target/riscv: zfh: half-precision load and store frank.chang
2021-10-21 16:29 ` [PATCH v5 2/8] target/riscv: zfh: half-precision computational frank.chang
@ 2021-10-21 16:29 ` frank.chang
2021-10-21 16:29 ` [PATCH v5 4/8] target/riscv: zfh: half-precision floating-point compare frank.chang
` (5 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: frank.chang @ 2021-10-21 16:29 UTC (permalink / raw)
To: qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, qemu-devel,
Chih-Min Chao, Palmer Dabbelt, Alistair Francis, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/fpu_helper.c | 67 +++++
target/riscv/helper.h | 12 +
target/riscv/insn32.decode | 19 ++
target/riscv/insn_trans/trans_rvzfh.c.inc | 288 ++++++++++++++++++++++
target/riscv/translate.c | 10 +
5 files changed, 396 insertions(+)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 20bb89ad14f..2ed9b03193c 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -460,3 +460,70 @@ uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1)
float16 frs1 = check_nanbox_h(rs1);
return nanbox_h(float16_sqrt(frs1, &env->fp_status));
}
+
+target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ return float16_to_int32(frs1, &env->fp_status);
+}
+
+target_ulong helper_fcvt_wu_h(CPURISCVState *env, uint64_t rs1)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ return (int32_t)float16_to_uint32(frs1, &env->fp_status);
+}
+
+target_ulong helper_fcvt_l_h(CPURISCVState *env, uint64_t rs1)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ return float16_to_int64(frs1, &env->fp_status);
+}
+
+target_ulong helper_fcvt_lu_h(CPURISCVState *env, uint64_t rs1)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ return float16_to_uint64(frs1, &env->fp_status);
+}
+
+uint64_t helper_fcvt_h_w(CPURISCVState *env, target_ulong rs1)
+{
+ return nanbox_h(int32_to_float16((int32_t)rs1, &env->fp_status));
+}
+
+uint64_t helper_fcvt_h_wu(CPURISCVState *env, target_ulong rs1)
+{
+ return nanbox_h(uint32_to_float16((uint32_t)rs1, &env->fp_status));
+}
+
+uint64_t helper_fcvt_h_l(CPURISCVState *env, target_ulong rs1)
+{
+ return nanbox_h(int64_to_float16(rs1, &env->fp_status));
+}
+
+uint64_t helper_fcvt_h_lu(CPURISCVState *env, target_ulong rs1)
+{
+ return nanbox_h(uint64_to_float16(rs1, &env->fp_status));
+}
+
+uint64_t helper_fcvt_h_s(CPURISCVState *env, uint64_t rs1)
+{
+ float32 frs1 = check_nanbox_s(rs1);
+ return nanbox_h(float32_to_float16(frs1, true, &env->fp_status));
+}
+
+uint64_t helper_fcvt_s_h(CPURISCVState *env, uint64_t rs1)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ return nanbox_s(float16_to_float32(frs1, true, &env->fp_status));
+}
+
+uint64_t helper_fcvt_h_d(CPURISCVState *env, uint64_t rs1)
+{
+ return nanbox_h(float64_to_float16(rs1, true, &env->fp_status));
+}
+
+uint64_t helper_fcvt_d_h(CPURISCVState *env, uint64_t rs1)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ return float16_to_float64(frs1, true, &env->fp_status);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c6c0323fafc..b50672d1684 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -74,6 +74,18 @@ DEF_HELPER_FLAGS_3(fdiv_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fmin_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fmax_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_2(fsqrt_h, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_s_h, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_h_s, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_d_h, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_h_d, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_w_h, TCG_CALL_NO_RWG, tl, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_wu_h, TCG_CALL_NO_RWG, tl, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_l_h, TCG_CALL_NO_RWG, tl, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_lu_h, TCG_CALL_NO_RWG, tl, env, i64)
+DEF_HELPER_FLAGS_2(fcvt_h_w, TCG_CALL_NO_RWG, i64, env, tl)
+DEF_HELPER_FLAGS_2(fcvt_h_wu, TCG_CALL_NO_RWG, i64, env, tl)
+DEF_HELPER_FLAGS_2(fcvt_h_l, TCG_CALL_NO_RWG, i64, env, tl)
+DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl)
/* Special functions */
DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 66c231a3010..ba40f3e7f89 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -739,5 +739,24 @@ fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm
fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm
fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm
fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm
+fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r
+fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r
+fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r
fmin_h 0010110 ..... ..... 000 ..... 1010011 @r
fmax_h 0010110 ..... ..... 001 ..... 1010011 @r
+fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm
+fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm
+fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2
+fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm
+fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm
+fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
+
+# *** RV64 Zfh Extension (in addition to RV32 Zfh) ***
+fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
+fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 9764d76f8bc..d1250257666 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -171,6 +171,93 @@ static bool trans_fsqrt_h(DisasContext *ctx, arg_fsqrt_h *a)
return true;
}
+static bool trans_fsgnj_h(DisasContext *ctx, arg_fsgnj_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ if (a->rs1 == a->rs2) { /* FMOV */
+ gen_check_nanbox_h(cpu_fpr[a->rd], cpu_fpr[a->rs1]);
+ } else {
+ TCGv_i64 rs1 = tcg_temp_new_i64();
+ TCGv_i64 rs2 = tcg_temp_new_i64();
+
+ gen_check_nanbox_h(rs1, cpu_fpr[a->rs1]);
+ gen_check_nanbox_h(rs2, cpu_fpr[a->rs2]);
+
+ /* This formulation retains the nanboxing of rs2. */
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], rs2, rs1, 0, 15);
+ tcg_temp_free_i64(rs1);
+ tcg_temp_free_i64(rs2);
+ }
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsgnjn_h *a)
+{
+ TCGv_i64 rs1, rs2, mask;
+
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ rs1 = tcg_temp_new_i64();
+ gen_check_nanbox_h(rs1, cpu_fpr[a->rs1]);
+
+ if (a->rs1 == a->rs2) { /* FNEG */
+ tcg_gen_xori_i64(cpu_fpr[a->rd], rs1, MAKE_64BIT_MASK(15, 1));
+ } else {
+ rs2 = tcg_temp_new_i64();
+ gen_check_nanbox_h(rs2, cpu_fpr[a->rs2]);
+
+ /*
+ * Replace bit 15 in rs1 with inverse in rs2.
+ * This formulation retains the nanboxing of rs1.
+ */
+ mask = tcg_const_i64(~MAKE_64BIT_MASK(15, 1));
+ tcg_gen_not_i64(rs2, rs2);
+ tcg_gen_andc_i64(rs2, rs2, mask);
+ tcg_gen_and_i64(rs1, mask, rs1);
+ tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2);
+
+ tcg_temp_free_i64(mask);
+ tcg_temp_free_i64(rs2);
+ }
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fsgnjx_h(DisasContext *ctx, arg_fsgnjx_h *a)
+{
+ TCGv_i64 rs1, rs2;
+
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ rs1 = tcg_temp_new_i64();
+ gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]);
+
+ if (a->rs1 == a->rs2) { /* FABS */
+ tcg_gen_andi_i64(cpu_fpr[a->rd], rs1, ~MAKE_64BIT_MASK(15, 1));
+ } else {
+ rs2 = tcg_temp_new_i64();
+ gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]);
+
+ /*
+ * Xor bit 15 in rs1 with that in rs2.
+ * This formulation retains the nanboxing of rs1.
+ */
+ tcg_gen_andi_i64(rs2, rs2, MAKE_64BIT_MASK(15, 1));
+ tcg_gen_xor_i64(cpu_fpr[a->rd], rs1, rs2);
+
+ tcg_temp_free_i64(rs2);
+ }
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
static bool trans_fmin_h(DisasContext *ctx, arg_fmin_h *a)
{
REQUIRE_FPU;
@@ -192,3 +279,204 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a)
mark_fs_dirty(ctx);
return true;
}
+
+static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ mark_fs_dirty(ctx);
+
+ return true;
+}
+
+static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_d_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ mark_fs_dirty(ctx);
+
+
+ return true;
+}
+
+static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_h_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ mark_fs_dirty(ctx);
+
+ return true;
+}
+
+static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+ REQUIRE_EXT(ctx, RVD);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_h_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
+
+ mark_fs_dirty(ctx);
+
+ return true;
+}
+
+static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_w_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_w_h(dest, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_fcvt_wu_h(DisasContext *ctx, arg_fcvt_wu_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_wu_h(dest, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_fcvt_h_w(DisasContext *ctx, arg_fcvt_h_w *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_h_w(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_h_wu(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+
+#if defined(TARGET_RISCV64)
+ /* 16 bits -> 64 bits */
+ tcg_gen_ext16s_tl(dest, cpu_fpr[a->rs1]);
+#else
+ /* 16 bits -> 32 bits */
+ tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]);
+ tcg_gen_ext16s_tl(dest, dest);
+#endif
+
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);
+
+ tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
+ gen_nanbox_h(cpu_fpr[a->rd], cpu_fpr[a->rd]);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_l_h(DisasContext *ctx, arg_fcvt_l_h *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_h(dest, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_fcvt_lu_h(DisasContext *ctx, arg_fcvt_lu_h *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_h(dest, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_fcvt_h_l(DisasContext *ctx, arg_fcvt_h_l *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_h_l(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
+
+static bool trans_fcvt_h_lu(DisasContext *ctx, arg_fcvt_h_lu *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv t0 = get_gpr(ctx, a->rs1, EXT_SIGN);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_h_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+ mark_fs_dirty(ctx);
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ad963d1898f..e6643a7d777 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -141,6 +141,16 @@ static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
*
* Here, the result is always nan-boxed, even the canonical nan.
*/
+static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
+{
+ TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull);
+ TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull);
+
+ tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
+ tcg_temp_free_i64(t_max);
+ tcg_temp_free_i64(t_nan);
+}
+
static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
{
TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 4/8] target/riscv: zfh: half-precision floating-point compare
[not found] <20211021162956.2772656-1-frank.chang@sifive.com>
` (2 preceding siblings ...)
2021-10-21 16:29 ` [PATCH v5 3/8] target/riscv: zfh: half-precision convert and move frank.chang
@ 2021-10-21 16:29 ` frank.chang
2021-10-21 16:29 ` [PATCH v5 5/8] target/riscv: zfh: half-precision floating-point classify frank.chang
` (4 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: frank.chang @ 2021-10-21 16:29 UTC (permalink / raw)
To: qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, qemu-devel,
Chih-Min Chao, Palmer Dabbelt, Alistair Francis, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/fpu_helper.c | 21 +++++++++++++
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvzfh.c.inc | 37 +++++++++++++++++++++++
4 files changed, 64 insertions(+)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 2ed9b03193c..ec2009ee65b 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -461,6 +461,27 @@ uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1)
return nanbox_h(float16_sqrt(frs1, &env->fp_status));
}
+target_ulong helper_fle_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ float16 frs2 = check_nanbox_h(rs2);
+ return float16_le(frs1, frs2, &env->fp_status);
+}
+
+target_ulong helper_flt_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ float16 frs2 = check_nanbox_h(rs2);
+ return float16_lt(frs1, frs2, &env->fp_status);
+}
+
+target_ulong helper_feq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ float16 frs2 = check_nanbox_h(rs2);
+ return float16_eq_quiet(frs1, frs2, &env->fp_status);
+}
+
target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1)
{
float16 frs1 = check_nanbox_h(rs1);
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index b50672d1684..9c89521d4ad 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -74,6 +74,9 @@ DEF_HELPER_FLAGS_3(fdiv_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fmin_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(fmax_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_2(fsqrt_h, TCG_CALL_NO_RWG, i64, env, i64)
+DEF_HELPER_FLAGS_3(fle_h, TCG_CALL_NO_RWG, tl, env, i64, i64)
+DEF_HELPER_FLAGS_3(flt_h, TCG_CALL_NO_RWG, tl, env, i64, i64)
+DEF_HELPER_FLAGS_3(feq_h, TCG_CALL_NO_RWG, tl, env, i64, i64)
DEF_HELPER_FLAGS_2(fcvt_s_h, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(fcvt_h_s, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(fcvt_d_h, TCG_CALL_NO_RWG, i64, env, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ba40f3e7f89..3906c9fb201 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -751,6 +751,9 @@ fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm
fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm
fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm
fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2
+feq_h 1010010 ..... ..... 010 ..... 1010011 @r
+flt_h 1010010 ..... ..... 001 ..... 1010011 @r
+fle_h 1010010 ..... ..... 000 ..... 1010011 @r
fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm
fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm
fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index d1250257666..8d0959a6671 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -335,6 +335,43 @@ static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a)
return true;
}
+static bool trans_feq_h(DisasContext *ctx, arg_feq_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+
+ gen_helper_feq_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
+static bool trans_flt_h(DisasContext *ctx, arg_flt_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+
+ gen_helper_flt_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool trans_fle_h(DisasContext *ctx, arg_fle_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+
+ gen_helper_fle_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_w_h *a)
{
REQUIRE_FPU;
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 5/8] target/riscv: zfh: half-precision floating-point classify
[not found] <20211021162956.2772656-1-frank.chang@sifive.com>
` (3 preceding siblings ...)
2021-10-21 16:29 ` [PATCH v5 4/8] target/riscv: zfh: half-precision floating-point compare frank.chang
@ 2021-10-21 16:29 ` frank.chang
2021-10-21 16:29 ` [PATCH v5 6/8] target/riscv: zfh: add Zfh cpu property frank.chang
` (3 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: frank.chang @ 2021-10-21 16:29 UTC (permalink / raw)
To: qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, qemu-devel,
Chih-Min Chao, Palmer Dabbelt, Alistair Francis, Kito Cheng
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/fpu_helper.c | 6 ++++++
target/riscv/helper.h | 1 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvzfh.c.inc | 12 ++++++++++++
4 files changed, 20 insertions(+)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index ec2009ee65b..388e23ca670 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -482,6 +482,12 @@ target_ulong helper_feq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2)
return float16_eq_quiet(frs1, frs2, &env->fp_status);
}
+target_ulong helper_fclass_h(uint64_t rs1)
+{
+ float16 frs1 = check_nanbox_h(rs1);
+ return fclass_h(frs1);
+}
+
target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1)
{
float16 frs1 = check_nanbox_h(rs1);
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 9c89521d4ad..d25cf725c57 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -89,6 +89,7 @@ DEF_HELPER_FLAGS_2(fcvt_h_w, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_h_wu, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_h_l, TCG_CALL_NO_RWG, i64, env, tl)
DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl)
+DEF_HELPER_FLAGS_1(fclass_h, TCG_CALL_NO_RWG_SE, tl, i64)
/* Special functions */
DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3906c9fb201..6c4cde216bc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -754,6 +754,7 @@ fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2
feq_h 1010010 ..... ..... 010 ..... 1010011 @r
flt_h 1010010 ..... ..... 001 ..... 1010011 @r
fle_h 1010010 ..... ..... 000 ..... 1010011 @r
+fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2
fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm
fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm
fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 8d0959a6671..0549e25fb45 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -372,6 +372,18 @@ static bool trans_fle_h(DisasContext *ctx, arg_fle_h *a)
return true;
}
+static bool trans_fclass_h(DisasContext *ctx, arg_fclass_h *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFH(ctx);
+
+ TCGv dest = dest_gpr(ctx, a->rd);
+
+ gen_helper_fclass_h(dest, cpu_fpr[a->rs1]);
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_w_h *a)
{
REQUIRE_FPU;
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 6/8] target/riscv: zfh: add Zfh cpu property
[not found] <20211021162956.2772656-1-frank.chang@sifive.com>
` (4 preceding siblings ...)
2021-10-21 16:29 ` [PATCH v5 5/8] target/riscv: zfh: half-precision floating-point classify frank.chang
@ 2021-10-21 16:29 ` frank.chang
2021-10-21 16:29 ` [PATCH v5 7/8] target/riscv: zfh: implement zfhmin extension frank.chang
` (2 subsequent siblings)
8 siblings, 0 replies; 13+ messages in thread
From: frank.chang @ 2021-10-21 16:29 UTC (permalink / raw)
To: qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 788fa0b11c0..1b3a7784b06 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -617,6 +617,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+ DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 7/8] target/riscv: zfh: implement zfhmin extension
[not found] <20211021162956.2772656-1-frank.chang@sifive.com>
` (5 preceding siblings ...)
2021-10-21 16:29 ` [PATCH v5 6/8] target/riscv: zfh: add Zfh cpu property frank.chang
@ 2021-10-21 16:29 ` frank.chang
2021-10-21 16:29 ` [PATCH v5 8/8] target/riscv: zfh: add Zfhmin cpu property frank.chang
2021-11-02 14:07 ` [PATCH v5 0/8] target/riscv: support Zfh, Zfhmin extension v0.1 Frank Chang
8 siblings, 0 replies; 13+ messages in thread
From: frank.chang @ 2021-10-21 16:29 UTC (permalink / raw)
To: qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson, qemu-devel,
Chih-Min Chao, Alistair Francis, Palmer Dabbelt, Kito Cheng
From: Frank Chang <frank.chang@sifive.com>
Zfhmin extension is a subset of Zfh extension, consisting only of data
transfer and conversion instructions.
If enabled, only the following instructions from Zfh extension are
included:
* flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s
* If D extension is present: fcvt.d.h, fcvt.h.d
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_rvzfh.c.inc | 22 ++++++++++++++--------
target/riscv/translate.c | 2 ++
3 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index da3c436987c..8b93e25a270 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -300,6 +300,7 @@ struct RISCVCPU {
bool ext_ifencei;
bool ext_icsr;
bool ext_zfh;
+ bool ext_zfhmin;
char *priv_spec;
char *user_spec;
diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc
index 0549e25fb45..5a7cac89585 100644
--- a/target/riscv/insn_trans/trans_rvzfh.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfh.c.inc
@@ -22,13 +22,19 @@
} \
} while (0)
+#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \
+ if (!(ctx->ext_zfh || ctx->ext_zfhmin)) { \
+ return false; \
+ } \
+} while (0)
+
static bool trans_flh(DisasContext *ctx, arg_flh *a)
{
TCGv_i64 dest;
TCGv t0;
REQUIRE_FPU;
- REQUIRE_ZFH(ctx);
+ REQUIRE_ZFH_OR_ZFHMIN(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
if (a->imm) {
@@ -50,7 +56,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
TCGv t0;
REQUIRE_FPU;
- REQUIRE_ZFH(ctx);
+ REQUIRE_ZFH_OR_ZFHMIN(ctx);
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
if (a->imm) {
@@ -283,7 +289,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a)
static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
{
REQUIRE_FPU;
- REQUIRE_ZFH(ctx);
+ REQUIRE_ZFH_OR_ZFHMIN(ctx);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_s_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
@@ -296,7 +302,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
{
REQUIRE_FPU;
- REQUIRE_ZFH(ctx);
+ REQUIRE_ZFH_OR_ZFHMIN(ctx);
REQUIRE_EXT(ctx, RVD);
gen_set_rm(ctx, a->rm);
@@ -311,7 +317,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
{
REQUIRE_FPU;
- REQUIRE_ZFH(ctx);
+ REQUIRE_ZFH_OR_ZFHMIN(ctx);
gen_set_rm(ctx, a->rm);
gen_helper_fcvt_h_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]);
@@ -324,7 +330,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a)
{
REQUIRE_FPU;
- REQUIRE_ZFH(ctx);
+ REQUIRE_ZFH_OR_ZFHMIN(ctx);
REQUIRE_EXT(ctx, RVD);
gen_set_rm(ctx, a->rm);
@@ -441,7 +447,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a)
static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
{
REQUIRE_FPU;
- REQUIRE_ZFH(ctx);
+ REQUIRE_ZFH_OR_ZFHMIN(ctx);
TCGv dest = dest_gpr(ctx, a->rd);
@@ -461,7 +467,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a)
{
REQUIRE_FPU;
- REQUIRE_ZFH(ctx);
+ REQUIRE_ZFH_OR_ZFHMIN(ctx);
TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e6643a7d777..66709091ca1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -71,6 +71,7 @@ typedef struct DisasContext {
bool virt_enabled;
bool ext_ifencei;
bool ext_zfh;
+ bool ext_zfhmin;
bool hlsx;
/* vector extension */
bool vill;
@@ -620,6 +621,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
ctx->ext_zfh = cpu->cfg.ext_zfh;
+ ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
ctx->vlen = cpu->cfg.vlen;
ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 8/8] target/riscv: zfh: add Zfhmin cpu property
[not found] <20211021162956.2772656-1-frank.chang@sifive.com>
` (6 preceding siblings ...)
2021-10-21 16:29 ` [PATCH v5 7/8] target/riscv: zfh: implement zfhmin extension frank.chang
@ 2021-10-21 16:29 ` frank.chang
2021-11-02 14:07 ` [PATCH v5 0/8] target/riscv: support Zfh, Zfhmin extension v0.1 Frank Chang
8 siblings, 0 replies; 13+ messages in thread
From: frank.chang @ 2021-10-21 16:29 UTC (permalink / raw)
To: qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Bin Meng, Alistair Francis,
qemu-devel
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1b3a7784b06..e6e3ef183ae 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -618,6 +618,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
+ DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
--
2.25.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v5 0/8] target/riscv: support Zfh, Zfhmin extension v0.1
[not found] <20211021162956.2772656-1-frank.chang@sifive.com>
` (7 preceding siblings ...)
2021-10-21 16:29 ` [PATCH v5 8/8] target/riscv: zfh: add Zfhmin cpu property frank.chang
@ 2021-11-02 14:07 ` Frank Chang
8 siblings, 0 replies; 13+ messages in thread
From: Frank Chang @ 2021-11-02 14:07 UTC (permalink / raw)
To: open list:RISC-V, qemu-devel@nongnu.org Developers,
Alistair Francis
[-- Attachment #1: Type: text/plain, Size: 2537 bytes --]
On Fri, Oct 22, 2021 at 12:30 AM <frank.chang@sifive.com> wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Zfh - Half width floating point
> Zfhmin - Subset of half width floating point
>
> Zfh, Zfhmin v0.1 is now in public review period and is required by
> RVV extension:
>
> https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/63gDCinXTwE/m/871Wm9XIBQAJ
>
> Zfh, Zfhmin can be enabled with -cpu option: Zfh=true and Zfhmin=true
> respectively.
>
> The port is available at:
> https://github.com/sifive/qemu/tree/zfh-upstream-v5
>
> Note: This patchset depends on another patchset listed in Based-on
> section below so it is not able to be built unless the patchset
> is applied.
>
> Changelog:
>
> v5:
> * Rebase on riscv-to-apply.next.
>
> v4:
> * Spilt Zfh, Zfhmin cpu properties related changes into individual
> patches.
>
> v3:
> * Use the renamed softfloat min/max APIs: *_minimum_number()
> and *_maximum_number().
> * Pick softfloat min/max APIs based on CPU privilege spec version.
> * Add braces for if statements in REQUIRE_ZFH() and
> REQUIRE_ZFH_OR_ZFHMIN().
> * Rearrange the positions of Zfh and Zfhmin cpu properties.
>
> v2:
> * Use {get,dest}_gpr APIs.
> * Add Zfhmin extension.
>
> Based-on: <20211021160847.2748577-1-frank.chang@sifive.com>
>
> Frank Chang (3):
> target/riscv: zfh: add Zfh cpu property
> target/riscv: zfh: implement zfhmin extension
> target/riscv: zfh: add Zfhmin cpu property
>
> Kito Cheng (5):
> target/riscv: zfh: half-precision load and store
> target/riscv: zfh: half-precision computational
> target/riscv: zfh: half-precision convert and move
> target/riscv: zfh: half-precision floating-point compare
> target/riscv: zfh: half-precision floating-point classify
>
> target/riscv/cpu.c | 2 +
> target/riscv/cpu.h | 2 +
> target/riscv/fpu_helper.c | 180 ++++++++
> target/riscv/helper.h | 29 ++
> target/riscv/insn32.decode | 38 ++
> target/riscv/insn_trans/trans_rvzfh.c.inc | 537 ++++++++++++++++++++++
> target/riscv/internals.h | 16 +
> target/riscv/translate.c | 20 +
> 8 files changed, 824 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rvzfh.c.inc
>
> --
> 2.25.1
>
>
Hi Alistair,
Is this one able to be merged to v6.2.0 as the soft feature freeze is due
today (2021-11-02).
I think this series has gotten all Reviewed-by.
Thanks,
Frank Chang
[-- Attachment #2: Type: text/html, Size: 3630 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread