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[176.184.26.1]) by smtp.gmail.com with ESMTPSA id p10-20020aa7c88a000000b00557075b4499sm1016313eds.58.2024.01.05.06.15.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Jan 2024 06:15:38 -0800 (PST) Message-ID: <07cfab6e-0671-45e6-80ba-f65500b41259@linaro.org> Date: Fri, 5 Jan 2024 15:15:37 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/9] intc/grlib_irqmp: implements multicore irq Content-Language: en-US To: =?UTF-8?Q?Cl=C3=A9ment_Chigot?= , qemu-devel@nongnu.org Cc: Frederic Konrad References: <20240105102421.163554-1-chigot@adacore.com> <20240105102421.163554-5-chigot@adacore.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240105102421.163554-5-chigot@adacore.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=philmd@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/1/24 11:24, Clément Chigot wrote: > Now there is an ncpus property, use it in order to deliver the IRQ to > multiple CPU. > > Co-developed-by: Frederic Konrad > Signed-off-by: Clément Chigot > --- > hw/intc/grlib_irqmp.c | 43 ++++++++++++++++++----------------- > hw/sparc/leon3.c | 3 ++- > include/hw/intc/grlib_irqmp.h | 2 +- > 3 files changed, 25 insertions(+), 23 deletions(-) > diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c > index 7b9809b81f..94d8ec94b0 100644 > --- a/hw/sparc/leon3.c > +++ b/hw/sparc/leon3.c > @@ -168,7 +168,8 @@ static void leon3_cache_control_int(CPUSPARCState *env) > > static void leon3_irq_ack(void *irq_manager, int intno) > { > - grlib_irqmp_ack((DeviceState *)irq_manager, intno); > + /* No SMP support yet. */ > + grlib_irqmp_ack((DeviceState *)irq_manager, 0, intno); This '0' was not obvious, now I figured, I suggest: /* No SMP support yet, only CPU #0 available so far. */ > }