* [Qemu-devel] [PATCH v1 1/1] tcg: mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITS
@ 2018-12-12 20:58 Alistair Francis
2018-12-12 21:46 ` Richard Henderson
2018-12-13 23:45 ` Richard Henderson
0 siblings, 2 replies; 3+ messages in thread
From: Alistair Francis @ 2018-12-12 20:58 UTC (permalink / raw)
To: qemu-devel@nongnu.org, aurelien@aurel32.net,
smarkovic@wavecomp.com, rth@twiddle.net
Cc: Alistair Francis, alistair23@gmail.com
Instead of hard coding 31 for the shift right use
TCG_TARGET_REG_BITS - 1.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tcg/mips/tcg-target.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index cff525373b..aa7cdabf23 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -796,7 +796,7 @@ static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
} else if (rl == al && rl == bl) {
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, 31);
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
} else {
tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
--
2.19.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH v1 1/1] tcg: mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITS
2018-12-12 20:58 [Qemu-devel] [PATCH v1 1/1] tcg: mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITS Alistair Francis
@ 2018-12-12 21:46 ` Richard Henderson
2018-12-13 23:45 ` Richard Henderson
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2018-12-12 21:46 UTC (permalink / raw)
To: Alistair Francis, qemu-devel@nongnu.org, aurelien@aurel32.net,
smarkovic@wavecomp.com
Cc: alistair23@gmail.com
On 12/12/18 2:58 PM, Alistair Francis wrote:
> Instead of hard coding 31 for the shift right use
> TCG_TARGET_REG_BITS - 1.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> tcg/mips/tcg-target.inc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/1] tcg: mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITS
2018-12-12 20:58 [Qemu-devel] [PATCH v1 1/1] tcg: mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITS Alistair Francis
2018-12-12 21:46 ` Richard Henderson
@ 2018-12-13 23:45 ` Richard Henderson
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2018-12-13 23:45 UTC (permalink / raw)
To: Alistair Francis, qemu-devel@nongnu.org, aurelien@aurel32.net,
smarkovic@wavecomp.com, rth@twiddle.net
Cc: alistair23@gmail.com
On 12/12/18 2:58 PM, Alistair Francis wrote:
> Instead of hard coding 31 for the shift right use
> TCG_TARGET_REG_BITS - 1.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> tcg/mips/tcg-target.inc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Queued.
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
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2018-12-12 20:58 [Qemu-devel] [PATCH v1 1/1] tcg: mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITS Alistair Francis
2018-12-12 21:46 ` Richard Henderson
2018-12-13 23:45 ` Richard Henderson
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