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[187.189.51.143]) by smtp.gmail.com with ESMTPSA id 5614622812f47-45598d6cbb2sm1497901b6e.21.2025.12.11.11.24.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Dec 2025 11:24:44 -0800 (PST) Message-ID: <081b44f3-48aa-4af3-a0d1-c8e5915d95e3@linaro.org> Date: Thu, 11 Dec 2025 13:24:42 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: Record AS in full tlb To: Mark Burton Cc: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier , =?UTF-8?Q?Alex_Benn=C3=A9e?= , Matheus Bernardino , Sid Manning , Brian Cain , QEMU Developers References: <0d3b4338-2c31-4e42-8a8e-319f3ad4029f@linaro.org> <2A86D9C4-7EA7-4275-943F-D75801B5539C@qti.qualcomm.com> From: Richard Henderson Content-Language: en-US In-Reply-To: <2A86D9C4-7EA7-4275-943F-D75801B5539C@qti.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/11/25 12:49, Mark Burton wrote: >> Adding the as to CPUTLBEntryFull is unnecessary because >> >> (1) Each CPUTLB, and thus each CPUTLBEntryFull, is private to the cpu. >> (2) Each CPUTLBEntryFull contains the MemTxAttrs for the access. >> >> Thus the AddressSpace is purely a function of (cpu, attrs). > > The issue is, it would seem, it is also a function of the lookup provided by an IOMMU access - that kindly provides an address space independent of any CPU. No, it really isn't. Because you think that, it seems like you're doing something wrong with IOMMU accesses. Since I don't know the wider context of the query means I don't know how to help you further. My shot in the dark: there is a flush that's supposed to happen for changes to a cpu's address space. There are plenty of ways in which this happens, e.g. x86 a20 translation line and pci bar changes. I forget the exact details when it comes to IOMMU, but there must be something related when translations change. The actual tcg flush will happen via the MemoryListener interface. r~