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Thu, 09 Oct 2025 10:43:13 -0700 (PDT) Received: from [192.168.0.4] ([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034f8770dsm34334805ad.117.2025.10.09.10.43.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Oct 2025 10:43:13 -0700 (PDT) Message-ID: <081b5886-56de-4037-9be3-5f60345bf5b5@linaro.org> Date: Thu, 9 Oct 2025 10:43:11 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 10/73] target/arm: Expand CPUARMState.exception.syndrome to 64 bits To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier References: <20251008215613.300150-1-richard.henderson@linaro.org> <20251008215613.300150-11-richard.henderson@linaro.org> From: Richard Henderson Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/9/25 07:14, Philippe Mathieu-Daudé wrote: > Hi, > > On 8/10/25 23:55, Richard Henderson wrote: >> This will be used for storing the ISS2 portion of the >> ESR_ELx registers in aarch64 state.  Re-order the fsr >> member to eliminate two structure holes. >> >> Drop the comment about "if we implement EL2" since we >> have already done so. >> >> Reviewed-by: Pierrick Bouvier >> Signed-off-by: Richard Henderson >> --- >>   target/arm/cpu.h     |  7 ++----- >>   target/arm/helper.c  |  2 +- >>   target/arm/machine.c | 32 +++++++++++++++++++++++++++++++- >>   3 files changed, 34 insertions(+), 7 deletions(-) >> >> diff --git a/target/arm/cpu.h b/target/arm/cpu.h >> index c9ea160d03..04b57f1dc5 100644 >> --- a/target/arm/cpu.h >> +++ b/target/arm/cpu.h >> @@ -633,13 +633,10 @@ typedef struct CPUArchState { >>        * entry process. >>        */ >>       struct { >> -        uint32_t syndrome; /* AArch64 format syndrome register */ >> -        uint32_t fsr; /* AArch32 format fault status register info */ >> +        uint64_t syndrome; /* AArch64 format syndrome register */ >>           uint64_t vaddress; /* virtual addr associated with exception, if any */ >> +        uint32_t fsr; /* AArch32 format fault status register info */ >>           uint32_t target_el; /* EL the exception should be targeted for */ >> -        /* If we implement EL2 we will also need to store information >> -         * about the intermediate physical address for stage 2 faults. >> -         */ >>       } exception; > > >> diff --git a/target/arm/machine.c b/target/arm/machine.c >> index 6666a0c50c..ce20b46f50 100644 >> --- a/target/arm/machine.c >> +++ b/target/arm/machine.c >> @@ -848,6 +848,23 @@ static const VMStateInfo vmstate_powered_off = { >>       .put = put_power, >>   }; >> +static bool syndrome64_needed(void *opaque) >> +{ >> +    ARMCPU *cpu = opaque; >> +    return cpu->env.exception.syndrome > UINT32_MAX; > > Hmm... > >> +} >> + >> +static const VMStateDescription vmstate_syndrome64 = { >> +    .name = "cpu/syndrome64", >> +    .version_id = 1, >> +    .minimum_version_id = 1, >> +    .needed = syndrome64_needed, > > Why not simply add a new description for the high bits and > always migrate? > >        .info = &vmstate_info_uint32, >        .offset = offsetofhigh32(ARMCPU, env.exception.syndrome), > >> +    .fields = (const VMStateField[]) { >> +        VMSTATE_UINT64(env.exception.syndrome, ARMCPU), >> +        VMSTATE_END_OF_LIST() >> +    }, >> +}; >> + Because that's more complicated, IMO. r~