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([2602:ae:154e:e201:72e2:2d06:c2b1:b106]) by smtp.gmail.com with ESMTPSA id r19-20020a170902be1300b0016bdf2220desm15015411pls.263.2022.08.11.10.01.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Aug 2022 10:01:54 -0700 (PDT) Message-ID: <08433cdd-465b-eb40-0177-6de47475d29c@linaro.org> Date: Thu, 11 Aug 2022 10:01:52 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH for-7.1] target/arm: Don't report Statistical Profiling Extension in ID registers Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Zenghui Yu References: <20220811131127.947334-1-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220811131127.947334-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/11/22 06:11, Peter Maydell wrote: > The newly added neoverse-n1 CPU has ID register values which indicate > the presence of the Statistical Profiling Extension, because the real > hardware has this feature. QEMU's TCG emulation does not yet > implement SPE, though (not even as a minimal stub implementation), so > guests will crash if they try to use it because the SPE system > registers don't exist. > > Force ID_AA64DFR0_EL1.PMSVer to 0 in CPU realize for TCG, so that > we don't advertise to the guest a feature that doesn't exist. > > (We could alternatively do this by editing the value that > aarch64_neoverse_n1_initfn() sets for this ID register, but > suppressing the field in realize means we won't re-introduce this bug > when we add other CPUs that have SPE in hardware, such as the > Neoverse-V1.) > > An example of a non-booting guest is current mainline Linux (5.19), > when booting in EL2 on the virt board (ie with -machine > virtualization=on). > > Reported-by: Zenghui Yu > Signed-off-by: Peter Maydell > --- > I think we missed this earlier because it happens not to be hit if > you boot the kernel into EL1, only EL2. > --- > target/arm/cpu.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) Reviewed-by: Richard Henderson r~