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[66.75.72.126]) by smtp.gmail.com with ESMTPSA id l190sm19326117pfl.205.2021.01.19.09.46.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Jan 2021 09:46:45 -0800 (PST) Subject: Re: [PATCH v2 03/22] tcg/i386: Split out target constraints to tcg-target-con-str.h To: Peter Maydell References: <20210115210456.1053477-1-richard.henderson@linaro.org> <20210115210456.1053477-4-richard.henderson@linaro.org> From: Richard Henderson Message-ID: <0852e1ab-bf36-09cf-81fe-4c6349a2cdfc@linaro.org> Date: Tue, 19 Jan 2021 07:46:42 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/19/21 4:38 AM, Peter Maydell wrote: >> - case 's': >> - /* qemu_st8_i32 data constraint */ >> - ct->regs = 0xf; >> -#ifdef CONFIG_SOFTMMU >> - tcg_regset_reset_reg(ct->regs, TCG_REG_L0); >> - tcg_regset_reset_reg(ct->regs, TCG_REG_L1); >> -#endif >> - break; > > But in the old code the 's' constraint is 0xf for both > x86-64 and i386. That's perhaps laziness, or simply the lack of names in the old code. It logically should be BYTEL, because that's where byte stores go from. In the end it doesn't matter, because this constraint is *only* used by i386. The opcode INDEX_op_qemu_st8_i32 is not used by x86_64 at all. See TCG_TARGET_HAS_qemu_st8_i32 in tcg-target.h. r~