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References: <20180223153636.29809-1-alex.bennee@linaro.org>
	<20180223153636.29809-15-alex.bennee@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <0882ecdd-b31d-aa04-f80d-2404ead313be@linaro.org>
Date: Fri, 23 Feb 2018 16:03:41 -0800
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Subject: Re: [Qemu-devel] [PATCH v3 14/31] arm/translate-a64: add FP16
 FMULX/MLS/FMLA to simd_indexed
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To: =?UTF-8?Q?Alex_Benn=c3=a9e?= <alex.bennee@linaro.org>, qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>

On 02/23/2018 07:36 AM, Alex Bennée wrote:
>      case 0x9: /* FMUL, FMULX */
> -        if (!extract32(size, 1, 1)) {
> +        if (size == 1 ||
> +            (size < 2 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) {
>              unallocated_encoding(s);

You get to drop the check here...

> +        case 0: /* half precision */
> +            size = MO_16;
> +            index = h << 2 | l << 1 | m;
> +            is_fp16 = true;
> +            if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
> +                break;
> +            }

... because you added it here instead.


r~