From: Richard Henderson <richard.henderson@linaro.org>
To: Weiwei Li <liweiwei@iscas.ac.cn>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com
Subject: Re: [PATCH v2 4/5] target/riscv: Add support for PC-relative translation
Date: Wed, 29 Mar 2023 09:27:01 -0700 [thread overview]
Message-ID: <08b81942-a356-51c2-9de1-6e057a2ca8b1@linaro.org> (raw)
In-Reply-To: <20230329032346.55185-5-liweiwei@iscas.ac.cn>
On 3/28/23 20:23, Weiwei Li wrote:
> static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
> {
> - gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
> + assert(ctx->pc_save != -1);
> + if (tb_cflags(ctx->base.tb) & CF_PCREL) {
> + TCGv target_pc = tcg_temp_new();
dest_gpr(s, a->rd)
> @@ -51,26 +59,43 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
> static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
> {
> TCGLabel *misaligned = NULL;
> + TCGv succ_pc = tcg_temp_new();
succ_pc can by null for !CF_PCREL...
> + TCGv target_pc = tcg_temp_new();
> +
> + if (tb_cflags(ctx->base.tb) & CF_PCREL) {
> + tcg_gen_addi_tl(succ_pc, cpu_pc, ctx->pc_succ_insn - ctx->pc_save);
> + }
... or initialized like
} else {
succ_pc = tcg_constant_tl(ctx->pc_succ_insn);
}
> - gen_set_pc(ctx, cpu_pc);
> if (!has_ext(ctx, RVC)) {
> TCGv t0 = tcg_temp_new();
>
> misaligned = gen_new_label();
> - tcg_gen_andi_tl(t0, cpu_pc, 0x2);
> + tcg_gen_andi_tl(t0, target_pc, 0x2);
> tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
> }
...
> if (misaligned) {
> gen_set_label(misaligned);
> - gen_exception_inst_addr_mis(ctx);
> + gen_exception_inst_addr_mis(ctx, target_pc);
> }
This is what I expected from patch 3: cpu_pc is unchanged, with the new (incorrect)
address passed to inst_addr_mis for assigning to badaddr. Bug being fixed here, thus
should really be a separate patch.
> @@ -172,7 +197,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
> if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
> /* misaligned */
> gen_set_pc_imm(ctx, ctx->base.pc_next + a->imm);
> - gen_exception_inst_addr_mis(ctx);
> + gen_exception_inst_addr_mis(ctx, cpu_pc);
But this one's different and (probably) incorrect.
> @@ -552,13 +567,21 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
> if (!has_ext(ctx, RVC)) {
> if ((next_pc & 0x3) != 0) {
> gen_set_pc_imm(ctx, next_pc);
> - gen_exception_inst_addr_mis(ctx);
> + gen_exception_inst_addr_mis(ctx, cpu_pc);
Likewise.
> + assert(ctx->pc_save != -1);
> + if (tb_cflags(ctx->base.tb) & CF_PCREL) {
> + TCGv succ_pc = tcg_temp_new();
> + tcg_gen_addi_tl(succ_pc, cpu_pc, ctx->pc_succ_insn - ctx->pc_save);
> + gen_set_gpr(ctx, rd, succ_pc);
dest_gpr.
r~
next prev parent reply other threads:[~2023-03-29 16:27 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-29 3:23 [PATCH v2 0/5] target/riscv: Fix pointer mask related support Weiwei Li
2023-03-29 3:23 ` [PATCH v2 1/5] target/riscv: Fix pointer mask transformation for vector address Weiwei Li
2023-03-29 3:23 ` [PATCH v2 2/5] target/riscv: Update cur_pmmask/base when xl changes Weiwei Li
2023-03-31 1:34 ` LIU Zhiwei
2023-03-29 3:23 ` [PATCH v2 3/5] target/riscv: Sync cpu_pc before update badaddr Weiwei Li
2023-03-29 15:33 ` Richard Henderson
2023-03-30 0:53 ` liweiwei
2023-03-31 6:13 ` LIU Zhiwei
2023-03-29 3:23 ` [PATCH v2 4/5] target/riscv: Add support for PC-relative translation Weiwei Li
2023-03-29 16:27 ` Richard Henderson [this message]
2023-03-30 1:09 ` liweiwei
2023-03-30 17:07 ` Richard Henderson
2023-03-29 3:23 ` [PATCH v2 5/5] target/riscv: Add pointer mask support for instruction fetch Weiwei Li
2023-03-29 16:36 ` Richard Henderson
2023-03-30 1:10 ` liweiwei
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