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Mon, 21 Jun 2021 16:30:28 -0700 (PDT) Received: from [192.168.1.11] ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id b10sm16386263pfi.122.2021.06.21.16.30.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Jun 2021 16:30:28 -0700 (PDT) Subject: Re: Denormal input handling To: Michael Morrell , "qemu-devel@nongnu.org" References: <30eafc8be31446f9aecbc40f487467e1@tachyum.com> From: Richard Henderson Message-ID: <08ba29ee-d5c0-8c61-0efc-4c03fe9da944@linaro.org> Date: Mon, 21 Jun 2021 16:30:26 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/21/21 4:13 PM, Michael Morrell wrote: > I have another couple of thoughts around input denormal handling. > > The first is straightforward.  I noticed that the Aarch64 port doesn't report input > denormals (I could not find any code which sets the IDC bit in the FPSR).  I found code in > the arm (not aarch64) port that sets other bits like IXC, but nothing for IDC.   Is that > simply because no one has bothered to add this support? It's because we failed to use symbolic constants. See vfp_exceptbits_from_host. Which *is* used for both aarch64 and arm. > The second concerns support for cases where multiple exception conditions occur.   I had > originally thought that denormal input handling would be orthogonal to everything else and > so a case like "sNaN  + denorm" would set both the invalid and input denormal flags or > "denorm / 0" would set both idivde by zero and input denormal, but I don't think that is > true for at least some architectures.  Perhaps some specialization is needed here? If you've got a specific example, we can look at it. There's no point adding specialization that isn't going to be used. r~