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([2804:431:c7c6:7ce4:b718:2cc0:32df:97ee]) by smtp.gmail.com with ESMTPSA id y18sm2462077qtx.19.2021.12.22.10.13.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Dec 2021 10:13:18 -0800 (PST) Message-ID: <08d94fa5-f88d-4cd7-e7c7-67322126927d@gmail.com> Date: Wed, 22 Dec 2021 15:13:15 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.0 Subject: Re: [PATCH 5/5] ppc/pnv: Attach PHB4 root port device when defaults are enabled Content-Language: en-US To: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org References: <20211222063817.1541058-1-clg@kaod.org> <20211222063817.1541058-6-clg@kaod.org> From: Daniel Henrique Barboza In-Reply-To: <20211222063817.1541058-6-clg@kaod.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::f2e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::f2e; envelope-from=danielhb413@gmail.com; helo=mail-qv1-xf2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.694, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/22/21 03:38, Cédric Le Goater wrote: > This cleanups the PHB4 model a bit more since the root port is an > independent device and it will ease our task when adding user created > PHB4s. > > Signed-off-by: Cédric Le Goater > --- Reviewed-by: Daniel Henrique Barboza > include/hw/pci-host/pnv_phb4.h | 2 -- > hw/pci-host/pnv_phb4.c | 11 ----------- > hw/ppc/pnv.c | 9 ++++++++- > 3 files changed, 8 insertions(+), 14 deletions(-) > > diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h > index 4a19338db35e..ea63df967678 100644 > --- a/include/hw/pci-host/pnv_phb4.h > +++ b/include/hw/pci-host/pnv_phb4.h > @@ -78,8 +78,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) > struct PnvPHB4 { > PCIExpressHost parent_obj; > > - PnvPHB4RootPort root; > - > uint32_t chip_id; > uint32_t phb_id; > > diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c > index 3b50a22b97cd..3b4758c42e26 100644 > --- a/hw/pci-host/pnv_phb4.c > +++ b/hw/pci-host/pnv_phb4.c > @@ -1158,12 +1158,6 @@ static void pnv_phb4_instance_init(Object *obj) > > /* XIVE interrupt source object */ > object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); > - > - /* Root Port */ > - object_initialize_child(obj, "root", &phb->root, TYPE_PNV_PHB4_ROOT_PORT); > - > - qdev_prop_set_int32(DEVICE(&phb->root), "addr", PCI_DEVFN(0, 0)); > - qdev_prop_set_bit(DEVICE(&phb->root), "multifunction", false); > } > > static void pnv_phb4_realize(DeviceState *dev, Error **errp) > @@ -1207,11 +1201,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) > pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb); > pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; > > - /* Add a single Root port */ > - qdev_prop_set_uint8(DEVICE(&phb->root), "chassis", phb->chip_id); > - qdev_prop_set_uint16(DEVICE(&phb->root), "slot", phb->phb_id); > - qdev_realize(DEVICE(&phb->root), BUS(pci->bus), &error_fatal); > - > /* Setup XIVE Source */ > if (phb->big_phb) { > nr_irqs = PNV_PHB4_MAX_INTs; > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 6edfd6876fd0..7a397698e984 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1403,7 +1403,7 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) > static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) > { > Pnv9Chip *chip9 = PNV9_CHIP(chip); > - int i; > + int i, j; > > for (i = 0; i < chip->num_pecs; i++) { > PnvPhb4PecState *pec = &chip9->pecs[i]; > @@ -1425,6 +1425,13 @@ static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) > > pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); > pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); > + > + for (j = 0; j < pec->num_stacks; j++) { > + PnvPHB4 *phb = &pec->stacks[j].phb; > + > + pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), phb->phb_id, > + TYPE_PNV_PHB4_ROOT_PORT); > + } > } > } > >