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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9b2654sm16699286f8f.41.2025.03.26.06.59.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Mar 2025 06:59:13 -0700 (PDT) Message-ID: <092113d0-9cd8-4384-b65a-46922239c794@redhat.com> Date: Wed, 26 Mar 2025 14:59:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 13/20] hw/arm/smmuv3-accel: Introduce helpers to batch and issue cache invalidations Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> <20250311141045.66620-14-shameerali.kolothum.thodi@huawei.com> From: Eric Auger In-Reply-To: <20250311141045.66620-14-shameerali.kolothum.thodi@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/11/25 3:10 PM, Shameer Kolothum wrote: > From: Nicolin Chen > > Inroduce an SMMUCommandBatch and some helpers to batch and issue the > commands. Currently separate out TLBI commands and device cache commands > to avoid some errata on certain versions of SMMUs. Later it should check > IIDR register to detect if underlying SMMU hw has such an erratum. > > Signed-off-by: Nicolin Chen > Signed-off-by: Shameer Kolothum > --- > hw/arm/smmuv3-accel.c | 69 ++++++++++++++++++++++++++++++++++++++++ > hw/arm/smmuv3-internal.h | 29 +++++++++++++++++ > 2 files changed, 98 insertions(+) > > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > index 76134d106a..09be838d22 100644 > --- a/hw/arm/smmuv3-accel.c > +++ b/hw/arm/smmuv3-accel.c > @@ -160,6 +160,75 @@ void smmuv3_accel_install_nested_ste(SMMUDevice *sdev, int sid) > nested_data.ste[0]); > } > > +/* Update batch->ncmds to the number of execute cmds */ > +int smmuv3_accel_issue_cmd_batch(SMMUState *bs, SMMUCommandBatch *batch) > +{ > + SMMUv3AccelState *s_accel = ARM_SMMUV3_ACCEL(bs); > + uint32_t total = batch->ncmds; > + IOMMUFDViommu *viommu_core; > + int ret; > + > + if (!bs->accel) { > + return 0; > + } > + > + if (!s_accel->viommu) { > + return 0; > + } > + viommu_core = &s_accel->viommu->core; > + ret = iommufd_backend_invalidate_cache(viommu_core->iommufd, > + viommu_core->viommu_id, > + IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3, > + sizeof(Cmd), &batch->ncmds, > + batch->cmds); > + if (total != batch->ncmds) { > + error_report("%s failed: ret=%d, total=%d, done=%d", > + __func__, ret, total, batch->ncmds); > + return ret; > + } > + > + batch->ncmds = 0; > + batch->dev_cache = false; > + return ret; > +} > + > +int smmuv3_accel_batch_cmds(SMMUState *bs, SMMUDevice *sdev, I think you shall document that sdev can be NULL and also when this helper shall be called with sdev != NULL Thanks Eric > + SMMUCommandBatch *batch, Cmd *cmd, > + uint32_t *cons, bool dev_cache) > +{ > + int ret; > + > + if (!bs->accel) { > + return 0; > + } > + > + if (sdev) { > + SMMUv3AccelDevice *accel_dev; > + accel_dev = container_of(sdev, SMMUv3AccelDevice, sdev); > + if (!accel_dev->s1_hwpt) { > + return 0; > + } > + } > + > + /* > + * Currently separate out dev_cache and hwpt for safety, which might > + * not be necessary if underlying HW SMMU does not have the errata. > + * > + * TODO check IIDR register values read from hw_info. > + */ > + if (batch->ncmds && (dev_cache != batch->dev_cache)) { > + ret = smmuv3_accel_issue_cmd_batch(bs, batch); > + if (ret) { > + *cons = batch->cons[batch->ncmds]; > + return ret; > + } > + } > + batch->dev_cache = dev_cache; > + batch->cmds[batch->ncmds] = *cmd; > + batch->cons[batch->ncmds++] = *cons; > + return 0; > +} > + > static bool > smmuv3_accel_dev_attach_viommu(SMMUv3AccelDevice *accel_dev, > HostIOMMUDeviceIOMMUFD *idev, Error **errp) > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index 46c8bcae14..4602ae6728 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -549,13 +549,42 @@ typedef struct CD { > uint32_t word[16]; > } CD; > > +/** > + * SMMUCommandBatch - batch of invalidation commands for smmuv3-accel > + * @cmds: Pointer to list of commands > + * @cons: Pointer to list of CONS corresponding to the commands > + * @ncmds: Total ncmds in the batch > + * @dev_cache: Issue to a device cache > + */ > +typedef struct SMMUCommandBatch { > + Cmd *cmds; > + uint32_t *cons; > + uint32_t ncmds; > + bool dev_cache; > +} SMMUCommandBatch; > + > int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, > SMMUEventInfo *event); > void smmuv3_flush_config(SMMUDevice *sdev); > > #if defined(CONFIG_ARM_SMMUV3_ACCEL) && defined(CONFIG_IOMMUFD) > +int smmuv3_accel_issue_cmd_batch(SMMUState *bs, SMMUCommandBatch *batch); > +int smmuv3_accel_batch_cmds(SMMUState *bs, SMMUDevice *sdev, > + SMMUCommandBatch *batch, Cmd *cmd, > + uint32_t *cons, bool dev_cache); > void smmuv3_accel_install_nested_ste(SMMUDevice *sdev, int sid); > #else > +static inline int smmuv3_accel_issue_cmd_batch(SMMUState *bs, > + SMMUCommandBatch *batch) > +{ > + return 0; > +} > +static inline int smmuv3_accel_batch_cmds(SMMUState *bs, SMMUDevice *sdev, > + SMMUCommandBatch *batch, Cmd *cmd, > + uint32_t *cons, bool dev_cache) > +{ > + return 0; > +} > static inline void smmuv3_accel_install_nested_ste(SMMUDevice *sdev, int sid) > { > }