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From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= <clg@kaod.org>
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Date: Fri, 7 Oct 2016 10:24:53 +0200
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Subject: Re: [Qemu-devel] [PATCH v4 03/20] ppc/pnv: add a core mask to
 PnvChip
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To: David Gibson <david@gibson.dropbear.id.au>, Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org

On 10/07/2016 07:11 AM, David Gibson wrote:
> On Fri, Oct 07, 2016 at 04:01:52PM +1100, Benjamin Herrenschmidt wrote:
>> On Fri, 2016-10-07 at 15:32 +1100, David Gibson wrote:
>>> On Mon, Oct 03, 2016 at 09:24:39AM +0200, C=E9dric Le Goater wrote:
>>>> This will be used to build real HW ids for the cores and enforce
>>> some
>>>> limits on the available cores per chip.
>>>
>>> Is there actually a practical reason to allow the user (or machine
>>> type) to override the default core mask?
>>
>> None other than mimmicing real HW ... some cores can be disabled
>> on some chips and we *might* want to mimmic that for some test
>> scenarios.
>=20
> Ok, sounds like a good enough reason to me.

There are really different layouts on the field. Here is a S824,
16 cores, 4 sockets, with these HW ids :

	0x4	0x4	0x5	0x4
	0x5	0x5	0xc	0x5
	0x6	0x6	0xd	0x6
	0xe	0xe	0xe	0xd

Long term, we will want to support unplug I suppose.
=09
C.