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([2602:ae:1541:f901:3369:815f:629b:7300]) by smtp.gmail.com with ESMTPSA id a12-20020a65640c000000b0050aeaf9f25csm21896676pgv.27.2023.03.29.08.33.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Mar 2023 08:33:16 -0700 (PDT) Message-ID: <092397fd-3b97-b866-6c72-aab132422f2f@linaro.org> Date: Wed, 29 Mar 2023 08:33:14 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v2 3/5] target/riscv: Sync cpu_pc before update badaddr Content-Language: en-US To: Weiwei Li , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com References: <20230329032346.55185-1-liweiwei@iscas.ac.cn> <20230329032346.55185-4-liweiwei@iscas.ac.cn> From: Richard Henderson In-Reply-To: <20230329032346.55185-4-liweiwei@iscas.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/28/23 20:23, Weiwei Li wrote: > We should sync cpu_pc before storing it into badaddr when mis-aligned > exception is triggered. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > --- > target/riscv/insn_trans/trans_rvi.c.inc | 1 + > target/riscv/translate.c | 1 + > 2 files changed, 2 insertions(+) Yes, badaddr should get the invalid pc, but surely epc should contain the pc of the branch instruction causing the fault. I thought that was the primary reason to handle this exception here, rather than at the start of the translation loop. r~ > > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc > index 4ad54e8a49..05d8b5d57f 100644 > --- a/target/riscv/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > @@ -171,6 +171,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) > > if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { > /* misaligned */ > + gen_set_pc_imm(ctx, ctx->base.pc_next + a->imm); > gen_exception_inst_addr_mis(ctx); > } else { > gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm); > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 0ee8ee147d..f7ddf4c50d 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -551,6 +551,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) > next_pc = ctx->base.pc_next + imm; > if (!has_ext(ctx, RVC)) { > if ((next_pc & 0x3) != 0) { > + gen_set_pc_imm(ctx, next_pc); > gen_exception_inst_addr_mis(ctx); > return; > }