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[176.131.223.129]) by smtp.gmail.com with ESMTPSA id x8-20020a170906298800b0099bcb44493fsm947897eje.147.2023.09.14.05.26.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Sep 2023 05:26:36 -0700 (PDT) Message-ID: <09413ec3-965d-8588-e0df-e8c4a6fa55b8@linaro.org> Date: Thu, 14 Sep 2023 14:26:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [RFC PATCH 2/3] {include/}hw/arm: refactor BSA/virt PPI logic Content-Language: en-US To: Leif Lindholm , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Radoslaw Biernacki , Peter Maydell , Marcin Juszkiewicz References: <20230914120124.55410-1-quic_llindhol@quicinc.com> <20230914120124.55410-3-quic_llindhol@quicinc.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230914120124.55410-3-quic_llindhol@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philmd@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.473, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 14/9/23 14:01, Leif Lindholm wrote: > GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31. > As in, PPI0 is INTID16 .. PPI15 is INTID31. > Arm's Base System Architecture specification (BSA) lists the mandated and > recommended private interrupt IDs by INTID, not by PPI index. But current > definitions in qemu define them by PPI index, complicating cross > referencing. > > Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value, > converting a PPI index to an INTID. > > Resolve this by redefining the BSA-allocated PPIs by their INTIDs, > inverting the logic of the PPI(x) macro and flipping where it is used. > > Signed-off-by: Leif Lindholm > --- > hw/arm/virt-acpi-build.c | 4 ++-- > hw/arm/virt.c | 9 +++++---- > include/hw/arm/bsa.h | 14 +++++++------- > 3 files changed, 14 insertions(+), 13 deletions(-) Isn't it simpler to reorder patches 1 <-> 2? (First fix PPI macro use within virt.c, then expose header)