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From: Richard Henderson <richard.henderson@linaro.org>
To: Tomoaki Kawada <i@yvt.jp>, qemu-devel@nongnu.org
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Subject: Re: [PATCH] target/rx: update PC correctly in wait instruction
Date: Sun, 17 Apr 2022 09:06:17 -0700	[thread overview]
Message-ID: <09609f99-dce7-5acc-062a-a55b161c0412@linaro.org> (raw)
In-Reply-To: <20220417060224.2131788-1-i@yvt.jp>

On 4/16/22 23:02, Tomoaki Kawada wrote:
> `cpu_pc` at this point does not necessary point to the current
> instruction (i.e., the wait instruction being translated), so it's
> incorrect to calculate the new value of `cpu_pc` based on this. It must
> be updated with `ctx->base.pc_next`, which contains the correct address
> of the next instruction.
> 
> This change fixes the wait instruction skipping the subsequent branch
> when used in an idle loop like this:
> 
>      0:  wait
>          bra.b 0b
>          brk   // should be unreachable
> 
> Signed-off-by: Tomoaki Kawada <i@yvt.jp>
> ---
>   target/rx/translate.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/rx/translate.c b/target/rx/translate.c
> index 5db8f79a82..f8812e7a6c 100644
> --- a/target/rx/translate.c
> +++ b/target/rx/translate.c
> @@ -2281,7 +2281,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a)
>   static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a)
>   {
>       if (is_privileged(ctx, 1)) {
> -        tcg_gen_addi_i32(cpu_pc, cpu_pc, 2);
> +        tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
>           gen_helper_wait(cpu_env);
>       }
>       return true;

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


  reply	other threads:[~2022-04-17 16:08 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-17  6:02 [PATCH] target/rx: update PC correctly in wait instruction Tomoaki Kawada
2022-04-17 16:06 ` Richard Henderson [this message]
2022-04-18 13:18 ` Yoshinori Sato
2022-04-21 17:10 ` Richard Henderson

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