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Thu, 10 Oct 2024 13:22:58 -0700 (PDT) Message-ID: <0961097b-d1be-4651-aa95-74d00b62a842@linaro.org> Date: Thu, 10 Oct 2024 17:22:54 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 11/12] target/mips: Remove target-specific code in mips_cpu_reset_hold() To: Richard Henderson , qemu-devel@nongnu.org Cc: Thomas Huth , Aurelien Jarno , =?UTF-8?Q?Herv=C3=A9_Poussineau?= , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen , Anton Johansson References: <20240930091101.40591-1-philmd@linaro.org> <20240930091101.40591-12-philmd@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/10/24 20:01, Richard Henderson wrote: > On 9/30/24 02:11, Philippe Mathieu-Daudé wrote: >> Since all code creating vCPUs now set the 'cpu-big-endian' property, >> we can remove the target-specific #ifdef'ry in mips_cpu_reset_hold(): >> the CP0C0_BE bit is set using the property cpu->is_big_endian value. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >>   target/mips/cpu.c | 3 --- >>   1 file changed, 3 deletions(-) >> >> diff --git a/target/mips/cpu.c b/target/mips/cpu.c >> index 02e2e72f2d..9724e71a5e 100644 >> --- a/target/mips/cpu.c >> +++ b/target/mips/cpu.c >> @@ -202,9 +202,6 @@ static void mips_cpu_reset_hold(Object *obj, >> ResetType type) >>       env->CP0_PRid = env->cpu_model->CP0_PRid; >>       env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0, >>                                    CP0C0_BE, 1, cpu->is_big_endian); >> -#if TARGET_BIG_ENDIAN >> -    env->CP0_Config0 |= (1 << CP0C0_BE); >> -#endif >>       env->CP0_Config1 = env->cpu_model->CP0_Config1; >>       env->CP0_Config2 = env->cpu_model->CP0_Config2; >>       env->CP0_Config3 = env->cpu_model->CP0_Config3; > > I think this must be merged into patch 8, or patch 8 doesn't work. Correct.