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From: Richard Henderson <richard.henderson@linaro.org>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org
Subject: Re: assert !temp_readonly(ts) in tcg_reg_alloc_op
Date: Fri, 7 Apr 2023 09:50:00 -0700	[thread overview]
Message-ID: <09705f7c-87ee-4bc2-f9d5-9045f272c4a7@linaro.org> (raw)
In-Reply-To: <CRQG87D3J96O.2610UOHM3V36V@wheely>

On 4/7/23 03:24, Nicholas Piggin wrote:
> On Fri Apr 7, 2023 at 7:02 PM AEST, Nicholas Piggin wrote:
>> I get a crash running a powerpc64 TCG machine on x86.
>>
>> It can be triggered by booting a custom vmlinux patched to use powerpc
>> prefix instructions and pcrel addressing, I don't know if that's related
>> or coincidence. I can give Linux patches or a vmlinux file to reproduce
>> if needed, or I can test patches quickly.
>>
>> The first bad commit is 7058ff5231a0 ("target/ppc: Avoid tcg_const_* in
>> translate.c")
> 
> This seems to do the trick:
> 
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 9d05357d03..23869fe6cb 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -1807,8 +1807,8 @@ static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
>           TCGv_i32 t2 = tcg_constant_i32(1);
>           TCGv_i32 t3 = tcg_constant_i32(0);
>           tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
> -        tcg_gen_remu_i32(t3, t0, t1);
> -        tcg_gen_extu_i32_tl(ret, t3);
> +        tcg_gen_remu_i32(t1, t0, t1);
> +        tcg_gen_extu_i32_tl(ret, t1);

Yes, that's the correct sort of fix.
Nit: slightly better as

     tcg_gen_remu_i32(ret, t0, t1);
     tcg_gen_extu_i32_tl(ret, ret);

where the no-op extu will not be emitted at all for ppc32.


r~


      reply	other threads:[~2023-04-07 16:50 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-07  9:02 assert !temp_readonly(ts) in tcg_reg_alloc_op Nicholas Piggin
2023-04-07 10:24 ` Nicholas Piggin
2023-04-07 16:50   ` Richard Henderson [this message]

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