From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Fabiano Rosas <farosas@suse.de>
Subject: Re: [PATCH v3 3/9] target/ppc: Fix instruction loading endianness in alignment interrupt
Date: Tue, 16 May 2023 12:46:55 -0300 [thread overview]
Message-ID: <099d7a72-4fda-5dff-2bad-509b48aab3a3@gmail.com> (raw)
In-Reply-To: <20230515092655.171206-4-npiggin@gmail.com>
Either this patch or patch 6 broke a gitlab KVM builder (cross-ppc64el-kvm-only)
as follows:
[1441/2019] Compiling C object libqemu-ppc-softmmu.fa.p/target_ppc_excp_helper.c.o
FAILED: libqemu-ppc-softmmu.fa.p/target_ppc_excp_helper.c.o
powerpc64le-linux-gnu-gcc -m64 -mlittle-endian -Ilibqemu-ppc-softmmu.fa.p -I. -I.. -Itarget/ppc -I../target/ppc -Iqapi -Itrace -Iui -Iui/shader -I/usr/include/pixman-1 -I/usr/include/capstone -I/usr/include/spice-server -I/usr/include/spice-1 -I/usr/include/glib-2.0 -I/usr/lib/powerpc64le-linux-gnu/glib-2.0/include -fdiagnostics-color=auto -Wall -Winvalid-pch -Werror -std=gnu11 -O2 -g -isystem /builds/danielhb/qemu/linux-headers -isystem linux-headers -iquote . -iquote /builds/danielhb/qemu -iquote /builds/danielhb/qemu/include -pthread -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -fno-strict-aliasing -fno-common -fwrapv -Wundef -Wwrite-strings -Wmissing-prototypes -Wstrict-prototypes -Wredundant-decls -Wold-style-declaration -Wold-style-definition -Wtype-limits -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wempty-body -Wnested-externs -Wendif-labels -Wexpansion-to-defined -Wimplicit-fallthrough=2 -Wmissing-format-attribute -Wno-missing-include-dirs -Wno-shift-negative-value -Wno-psabi -fstack-protector-strong -fPIE -isystem../linux-headers -isystemlinux-headers -DNEED_CPU_H '-DCONFIG_TARGET="ppc-softmmu-config-target.h"' '-DCONFIG_DEVICES="ppc-softmmu-config-devices.h"' -MD -MQ libqemu-ppc-softmmu.fa.p/target_ppc_excp_helper.c.o -MF libqemu-ppc-softmmu.fa.p/target_ppc_excp_helper.c.o.d -o libqemu-ppc-softmmu.fa.p/target_ppc_excp_helper.c.o -c ../target/ppc/excp_helper.c
../target/ppc/excp_helper.c:143:49: error: unknown type name ‘abi_ptr’; did you mean ‘si_ptr’?
143 | static uint32_t ppc_ldl_code(CPUArchState *env, abi_ptr addr)
| ^~~~~~~
| si_ptr
[1442/2019] Compiling C object libqemu-ppc-softmmu.fa.p/target_ppc_cpu-models.c.o
ninja: build stopped: subcommand failed.
make: *** [Makefile:165: run-ninja] Error 1
More details here:
https://gitlab.com/danielhb/qemu/-/jobs/4293326431
I suppose we're missing an ifdef somewhere to gate this code from KVM code. 'abi_ptr'
is a TCG pointer afaik.
Thanks,
Daniel
On 5/15/23 06:26, Nicholas Piggin wrote:
> powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
> after cpu_ldl_code(). This corrects DSISR bits in alignment
> interrupts when running in little endian mode.
>
> Reviewed-by: Fabiano Rosas <farosas@suse.de>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> Since v2: no change.
>
> target/ppc/excp_helper.c | 20 +++++++++++++++++++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 199328f4b6..bc2be4a726 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -133,6 +133,24 @@ static void dump_hcall(CPUPPCState *env)
> env->nip);
> }
>
> +/* Return true iff byteswap is needed in a scalar memop */
> +static inline bool need_byteswap(CPUArchState *env)
> +{
> + /* SOFTMMU builds TARGET_BIG_ENDIAN. Need to swap when MSR[LE] is set */
> + return !!(env->msr & ((target_ulong)1 << MSR_LE));
> +}
> +
> +static uint32_t ppc_ldl_code(CPUArchState *env, abi_ptr addr)
> +{
> + uint32_t insn = cpu_ldl_code(env, addr);
> +
> + if (need_byteswap(env)) {
> + insn = bswap32(insn);
> + }
> +
> + return insn;
> +}
> +
> static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp)
> {
> const char *es;
> @@ -3097,7 +3115,7 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
>
> /* Restore state and reload the insn we executed, for filling in DSISR. */
> cpu_restore_state(cs, retaddr);
> - insn = cpu_ldl_code(env, env->nip);
> + insn = ppc_ldl_code(env, env->nip);
>
> switch (env->mmu_model) {
> case POWERPC_MMU_SOFT_4xx:
next prev parent reply other threads:[~2023-05-16 15:48 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-15 9:26 [PATCH v3 0/9] target/ppc: Assorted ppc target fixes Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 1/9] target/ppc: Fix width of some 32-bit SPRs Nicholas Piggin
2023-05-15 10:14 ` Harsh Prateek Bora
2023-05-15 11:14 ` Nicholas Piggin
2023-05-15 11:43 ` Harsh Prateek Bora
2023-05-15 12:03 ` Mark Cave-Ayland
2023-05-15 12:51 ` Nicholas Piggin
2023-05-15 15:19 ` Nicholas Piggin
2023-05-16 7:02 ` Mark Cave-Ayland
2023-05-16 9:39 ` Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 2/9] target/ppc: Fix PMU MMCR0[PMCjCE] bit in hflags calculation Nicholas Piggin
2023-05-16 9:32 ` Daniel Henrique Barboza
2023-05-16 10:44 ` Nicholas Piggin
2023-05-16 11:07 ` Daniel Henrique Barboza
2023-05-15 9:26 ` [PATCH v3 3/9] target/ppc: Fix instruction loading endianness in alignment interrupt Nicholas Piggin
2023-05-16 15:46 ` Daniel Henrique Barboza [this message]
2023-05-15 9:26 ` [PATCH v3 4/9] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 5/9] target/ppc: Change partition-scope translate interface Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 6/9] target/ppc: Add SRR1 prefix indication to interrupt handlers Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 7/9] target/ppc: Implement HEIR SPR Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 8/9] target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 9/9] target/ppc: Better CTRL SPR implementation Nicholas Piggin
2023-05-27 18:05 ` [PATCH v3 0/9] target/ppc: Assorted ppc target fixes Daniel Henrique Barboza
2023-05-29 1:47 ` Nicholas Piggin
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