Re: [PATCH v2 2/2] aspeed: fix hardcode boot address 0

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

Hi Jamin,

On 7/2/24 20:52, Jamin Lin via wrote:
> In the previous design of ASPEED SOCs QEMU model, it set the boot
> address at "0" which was the hardcode setting for ast10x0, ast2600,
> ast2500 and ast2400.
> 
> According to the design of ast2700, it has bootmcu which is used for
> executing SPL and initialize DRAM, then, CPUs(cortex-a35)
> execute u-boot, kernel and rofs. QEMU will only support CPU(cortex-a35)
> parts and the boot address is "0x4 00000000" for ast2700.

This justification from here ...

> Therefore, fixed hardcode boot address 0.

... to here is still unclear. You provided an explanation in previous
patch, maybe worth including it in this description?

Otherwise for the code changes:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

> Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   hw/arm/aspeed.c             | 4 +++-
>   hw/arm/aspeed_ast2400.c     | 4 ++--
>   hw/arm/aspeed_ast2600.c     | 2 +-
>   include/hw/arm/aspeed_soc.h | 2 --
>   4 files changed, 6 insertions(+), 6 deletions(-)