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[2003:f6:af36:8f00:f7ba:e606:b15f:3bdb]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6d396208436sm58870806d6.56.2024.11.11.04.41.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Nov 2024 04:41:04 -0800 (PST) Date: Mon, 11 Nov 2024 13:40:59 +0100 (CET) From: Sebastian Ott To: qemu-devel@nongnu.org cc: Alex Williamson , Marcel Apfelbaum , "Michael S . Tsirkin" Subject: Re: [PATCH] pci: ensure valid link status bits for downstream ports In-Reply-To: <20241111123756.18393-1-sebott@redhat.com> Message-ID: <0a0049d2-7c72-5e5b-c35f-d777418f3eaa@redhat.com> References: <20241111123756.18393-1-sebott@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset=US-ASCII Received-SPF: pass client-ip=170.10.133.124; envelope-from=sebott@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.122, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, 11 Nov 2024, Sebastian Ott wrote: > PCI hotplug for downstream endpoints on arm fails because Linux' > PCIe hotplug driver doesn't like the QEMU provided LNKSTA: > > pcieport 0000:08:01.0: pciehp: Slot(2): Card present > pcieport 0000:08:01.0: pciehp: Slot(2): Link Up > pcieport 0000:08:01.0: pciehp: Slot(2): Cannot train link: status 0x2000 > > There's 2 cases where LNKSTA isn't setup properly: > * the downstream device has no express capability I stumbled over this while debugging - is a pci device attached to a pcie downstream even a valid usecase? > * max link width of the bridge is 0 MLW for the downstream is initialized with defaults but gets overwritten later because speed and width properties are 0. Dunno if that's the issue we should address? Sebastian