From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4FCF9C3DA60 for ; Thu, 18 Jul 2024 13:15:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1sUQxh-0001h8-I5; Thu, 18 Jul 2024 09:14:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUQxd-0001fE-RM; Thu, 18 Jul 2024 09:14:18 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1sUQxb-00029N-5U; Thu, 18 Jul 2024 09:14:17 -0400 Received: from mail.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4WPtYY3d52z4x0n; Thu, 18 Jul 2024 23:14:09 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4WPtYS2R47z4x0C; Thu, 18 Jul 2024 23:14:03 +1000 (AEST) Message-ID: <0a121e17-aede-4223-b8c0-91f202ff66ed@kaod.org> Date: Thu, 18 Jul 2024 15:14:01 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 10/15] hw/i2c/aspeed: support Tx/Rx buffer 64 bits address To: Jamin Lin , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , Alistair Francis , "open list:ASPEED BMCs" , "open list:All patches CC here" Cc: troy_lee@aspeedtech.com, yunlin.tang@aspeedtech.com References: <20240718064925.1846074-1-jamin_lin@aspeedtech.com> <20240718064925.1846074-11-jamin_lin@aspeedtech.com> Content-Language: en-US, fr From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= In-Reply-To: <20240718064925.1846074-11-jamin_lin@aspeedtech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=3riu=OS=kaod.org=clg@ozlabs.org; helo=mail.ozlabs.org X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/18/24 08:49, Jamin Lin wrote: > ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) > And the base address of dram is "0x4 00000000" which > is 64bits address. > > It have "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" > and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)" > to save the high part physical address of Tx/Rx buffer address > for master mode. > > It have "Slave DMA Mode Tx Buffer Base Address[39:32](0x68)" and > "Slave DMA Mode Rx Buffer Base Address[39:32](0x6C)" to > save the high part physical address of Tx/Rx buffer address > for slave mode. > > Ex: Tx buffer address for master mode [39:0] > The "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" > bits [7:0] which corresponds the bits [39:32] of the 64 bits address of > the Tx buffer address. > The "Master DMA Mode Tx Buffer Base Address(0x30)" bits [31:0] > which corresponds the bits [31:0] of the 64 bits address > of the Tx buffer address. > > Introduce a new has_dma64 class attribute and new registers of > new mode to support DMA 64 bits dram address. > Update new mode register number to 28. > > Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Thanks, C. > --- > hw/i2c/aspeed_i2c.c | 48 +++++++++++++++++++++++++++++++++++++ > include/hw/i2c/aspeed_i2c.h | 12 +++++++++- > 2 files changed, 59 insertions(+), 1 deletion(-) > > diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c > index 29d400ac93..b48f250e08 100644 > --- a/hw/i2c/aspeed_i2c.c > +++ b/hw/i2c/aspeed_i2c.c > @@ -140,6 +140,7 @@ static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus, hwaddr offset, > static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset, > unsigned size) > { > + AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); > uint64_t value = bus->regs[offset / sizeof(*bus->regs)]; > > switch (offset) { > @@ -170,6 +171,16 @@ static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *bus, hwaddr offset, > case A_I2CM_CMD: > value = SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus->bus)); > break; > + case A_I2CM_DMA_TX_ADDR_HI: > + case A_I2CM_DMA_RX_ADDR_HI: > + case A_I2CS_DMA_TX_ADDR_HI: > + case A_I2CS_DMA_RX_ADDR_HI: > + if (!aic->has_dma64) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n", > + __func__); > + value = -1; > + } > + break; > default: > qemu_log_mask(LOG_GUEST_ERROR, > "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset); > @@ -731,6 +742,42 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset, > qemu_log_mask(LOG_UNIMP, "%s: Slave mode DMA TX is not implemented\n", > __func__); > break; > + > + case A_I2CM_DMA_TX_ADDR_HI: > + if (!aic->has_dma64) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n", > + __func__); > + break; > + } > + bus->regs[R_I2CM_DMA_TX_ADDR_HI] = FIELD_EX32(value, > + I2CM_DMA_TX_ADDR_HI, > + ADDR_HI); > + break; > + case A_I2CM_DMA_RX_ADDR_HI: > + if (!aic->has_dma64) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n", > + __func__); > + break; > + } > + bus->regs[R_I2CM_DMA_RX_ADDR_HI] = FIELD_EX32(value, > + I2CM_DMA_RX_ADDR_HI, > + ADDR_HI); > + break; > + case A_I2CS_DMA_TX_ADDR_HI: > + qemu_log_mask(LOG_UNIMP, > + "%s: Slave mode DMA TX Addr high is not implemented\n", > + __func__); > + break; > + case A_I2CS_DMA_RX_ADDR_HI: > + if (!aic->has_dma64) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n", > + __func__); > + break; > + } > + bus->regs[R_I2CS_DMA_RX_ADDR_HI] = FIELD_EX32(value, > + I2CS_DMA_RX_ADDR_HI, > + ADDR_HI); > + break; > default: > qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", > __func__, offset); > @@ -1553,6 +1600,7 @@ static void aspeed_2700_i2c_class_init(ObjectClass *klass, void *data) > aic->bus_pool_base = aspeed_2500_i2c_bus_pool_base; > aic->has_dma = true; > aic->mem_size = 0x10000; > + aic->has_dma64 = true; > } > > static const TypeInfo aspeed_2700_i2c_info = { > diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h > index 4f23dc10c3..2c4c81bd20 100644 > --- a/include/hw/i2c/aspeed_i2c.h > +++ b/include/hw/i2c/aspeed_i2c.h > @@ -38,7 +38,7 @@ OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C) > #define ASPEED_I2C_SHARE_POOL_SIZE 0x800 > #define ASPEED_I2C_BUS_POOL_SIZE 0x20 > #define ASPEED_I2C_OLD_NUM_REG 11 > -#define ASPEED_I2C_NEW_NUM_REG 22 > +#define ASPEED_I2C_NEW_NUM_REG 28 > > #define A_I2CD_M_STOP_CMD BIT(5) > #define A_I2CD_M_RX_CMD BIT(3) > @@ -227,6 +227,15 @@ REG32(I2CS_DMA_LEN_STS, 0x4c) > FIELD(I2CS_DMA_LEN_STS, TX_LEN, 0, 13) > REG32(I2CC_DMA_ADDR, 0x50) > REG32(I2CC_DMA_LEN, 0x54) > +/* DMA 64bits */ > +REG32(I2CM_DMA_TX_ADDR_HI, 0x60) > + FIELD(I2CM_DMA_TX_ADDR_HI, ADDR_HI, 0, 7) > +REG32(I2CM_DMA_RX_ADDR_HI, 0x64) > + FIELD(I2CM_DMA_RX_ADDR_HI, ADDR_HI, 0, 7) > +REG32(I2CS_DMA_TX_ADDR_HI, 0x68) > + FIELD(I2CS_DMA_TX_ADDR_HI, ADDR_HI, 0, 7) > +REG32(I2CS_DMA_RX_ADDR_HI, 0x6c) > + FIELD(I2CS_DMA_RX_ADDR_HI, ADDR_HI, 0, 7) > > struct AspeedI2CState; > > @@ -292,6 +301,7 @@ struct AspeedI2CClass { > bool has_dma; > bool has_share_pool; > uint64_t mem_size; > + bool has_dma64; > }; > > static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s)